R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 541

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Rev.
1.00
REVISION HISTORY
Oct 27, 2006
Date
Page
218
222
228
231
232
242
245
246
249
259
275
276
289
Figure 14.75 Operating Example of PWM Mode → Figure 14.72 Operating
Example of PWM Mode replaced.
Figure 14.72 revised.
Figure 14.78 TRDSTR Register in Reset Synchronous PWM Mode → Figure
14.75 TRDSTR Register in Reset Synchronous PWM Mode replaced.
flag
Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode;
TRDGRA0 register; “(Output inversed every half period of TRDIOC0 pin)” →
“(Output inversed every period of TRDIOC0 and PWM pins)”,
TRDGRC0 register; “(Output inversed every half period of TRDIOC0 pin)” →
“(Output inversed every period of TRDIOC0 and PWM pins)” revised.
Table 14.31 Complementary PWM Mode Specifications, on the 3rd line from the
bottom;
Figure 14.85 TRDSTR Register in Complementary PWM Mode → Figure 14.85
TRDSTR Register in Complementary PWM Mode replaced.
corrected.
Figure 14.98 Operating Example of Complementary PWM Mode → Figure 14.95
Operating Example of Complementary PWM Mode replaced.
Table 14.33 PWM3 Mode Specifications, on the bottom line;
Figure 14.100 TRDSTR Register in PWM3 Mode → Figure 14.97 TRDSTR
Register in PWM3 Mode replaced.
corrected.
Figure 14.103 TRDOCR Register in PWM3 Mode → Figure 14.100 TRDOCR
Register in PWM3 Mode replaced.
NOTE2 added.
14.3.12.4 Count Source Switch;
14.3.12.7 Complementary PWM Mode, on the bottom line;
Figure 15.4 UiMR Register (i = 0 or 1);
corrected.
Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1);
Table 16.1 Mode Selections revised.
Timer RD Start Register
“TRDi count start bit
“i = 0 to 2, j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected.
Timer RD Start Register
“TRD1 count start bit
“j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected.
“TRD1 count start bit
“count clock source” → “count source” corrected.
“Do not use the TRDGRC0 register in complementary PWM mode.” deleted.
“Serial Interface mode select bit
UARTi Transmit/Receive Control Register 1 (i = 0 or 1) revised.
NOTE2 added.
Timer RD Start Register
R8C/22 Group, R8C/23 Group Hardware Manual
(4)
” corrected.
C - 18
(5)
(5)
(5)
” → “TRD1 count start flag
” → “TRD1 count start flag
” → “TRD1 count start flag
(1)
(1)
(1)
; “TRD0 count start bit
; TRD0 count start bit
; “TRD0 count start bit
Description
(2,4)
Summary
” → “Serial I/O mode select bit
(4)
(4)
(5)
(4)
(5)
(5)
” → “TRD0 count start flag
→ “TRD0 count start flag
” corrected.
” → “TRD0 count start
” corrected.
” corrected.
(2,4)
”
(4)
(4)
”
”