R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 408
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
18.6
Figure 18.18
Figure 18.19
18.6.1
The R8C/22 Group, R8C/23 Group contain a CAN module system clock selectable circuit. The CAN module
system clock can be selected by setting the CCLKR register and the BRP bit in the C0CINR register.
For the CCLKR register, refer to 10. Clock Generation Circuit.
Figure 18.18 shows a Block Diagram of CAN Module System Clock Generation Circuit.
f1
The bit time consists of the following four segments:
Figure 18.19 shows the Bit Timing.
Configuration of the CAN Module System Clock
•
•
•
•
The range of each segment:
Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay
on the CAN bus, the input comparator delay, and the output driver delay.
Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than expected, the
segment can become longer by the maximum of the value defined in SJW.
Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit falls
earlier than expected, the segment can become shorter by the maximum of the value defined in SJW.
Bit Timing Configuration
Divider of System Clock
fCAN
P
fCANCLK : CAN communication clock fCANCLK = fCAN/2 (P + 1)
Value : 1, 2, 4, 8, 16
CCLKR register
Block Diagram of CAN Module System Clock Generation Circuit
Bit Timing
CAN Module
SS
Page 386 of 501
: CAN module system clock
: The value written to the BRP bit in the C0CONR register. P = 0 to 15
Bit time = 8 to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
PTS
Divide-by 1 of XIN (undivided)
Divide-by 2 of XIN
Divide-by 4 of XIN
Divide-by 8 of XIN
Divide-by 16 of XIN
Bit time
Configuration of PBS1 and PBS2:
PBS1
Sampling point
SJW
fCAN
PBS1 > PBS2
PBS1 > SJW
PBS2 > 2 when SJW = 1
PBS2 > SJW when 2 < SJW < 4
Prescaler
1/2
PBS2
CAN module
Division by (P+1)
Prescaler for
Baud Rate
SJW
fCANCLK
18. CAN Module
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