R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 431
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
19.3
Figure 19.8
When the SMP bit in the ADCON2 register is set to 1 (with sample and hold function), A/D conversion rate per pin
increases. The sample and hold function is available in all operating modes. Start the A/D conversion after
selecting whether the sample and hold circuit is to be used or not.
Figure 19.8 shows the Timing Diagram of A/D Conversion.
Sample & hold
Sample & hold
Sample and Hold
disabled
enabled
Timing Diagram of A/D Conversion
Page 409 of 501
Conversion time at the 1st bit
Sampling time
Conversion time at the 1st bit
Sampling time
4ø AD cycle
4ø AD cycle
Comparison
Comparison
time
time
at the 2nd bit
Sampling time
2.5ø AD cycle
Comparison
time
at the 2nd bit
* Repeat until conversion ends
Comparison
Comparison
time
time
* Repeat until conversion ends
Sampling time
2.5ø AD cycle
Comparison
time
Comparison
time
19. A/D Converter
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