R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 443
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
20.4
Table 20.3
NOTE:
Operating Mode
Areas in which a Rewrite
Control Program Can be
Located
Areas in which a Rewrite
Control Program can be
Executed
Areas which can be
Rewritten
Software Command
Restriction
Modes After Program or
Erase
Modes After Read Status
Register
CPU Status During Auto-
write and Auto-erase
Flash Memory Status
Detection
Conditions for Transition to
Erase-suspend
Conditions for Transitions to
Program-suspend
CPU Clock
In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore,
the user ROM area can be rewritten directly while the MCU is mounted on a board without using such as a ROM
programmer. Execute the program and block erase commands only to each block in user ROM area.
When an interrupt request is generated during an erase operation in CPU rewrite mode, the flash module contains
an erase-suspend function which performs the interrupt process after the erase operation is halted temporarily.
During the erase-suspend, user ROM area can be read by a program.
When an interrupt request is generated during the auto-program operation in CPU rewrite mode, the flash module
contains a program-suspend function which performs the interrupt process after the auto-program operation
suspends. During the program-suspend, user ROM area can be read by a program.
CPU rewrite mode contains erase write 0 mode (EW0 mode) and erase write 1 mode (EW1 mode).
Table 20.3 lists the Differences between EW0 Mode and EW1 Mode.
1. When setting the FMR02 bit in the FMR0 register to 1 (rewrite enables) and rewriting block 0 is enabled by
setting the FMR15 bit in the FMR1 register to 0 (rewrite enables). Rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enables).
CPU Rewrite Mode
Item
Differences between EW0 Mode and EW1 Mode
Page 421 of 501
Single chip mode
User ROM area
Necessary to transfer to any areas
other than the flash memory (e.g.,
RAM) before executing
User ROM area
None
Read status register mode
Read status register mode
Operating
• Read the FMR00, FMR06, and
• Execute the read status register
Set the FMR40 and FMR41 bits in
the FMR4 register to 1 by a program.
Set the FMR40 and FMR42 bits in the
FMR4 register to 1 by a program.
5 MHz or below
FMR07 bits in the FMR0 register by
a program
command and read the SR7, SR5,
and SR4 bits in the status register.
EW0 Mode
Single chip mode
User ROM area
Executing directly in user ROM or RAM
area possible
User ROM area
• Program and block erase commands
• Read status register command
Read array mode
Do not execute this command
Hold state (I/O ports hold state
before the command is executed)
Read the FMR00, FMR06, and
FMR07 bits in the FMR0 register by a
program
The FMR40 bit in the FMR4 register
is set to 1 and the interrupt request of
the enabled maskable interrupt is
generated
The FMR40 bit in the FMR4 register is
set to 1 and the interrupt request of the
enabled maskable interrupt is generated
No restriction to the following (clock
frequency to be used)
Cannot be run on any block which
contains a rewrite control program
Cannot be executed
However, other than the blocks
which contain a rewrite control
program
(1)
EW1 Mode
20. Flash Memory
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