R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 365

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.3.3.5
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figure 16.39 and Figure 16.40 show the Operation Timing in Slave Receive Mode (I
The receive procedure and operation in slave receive mode are shown below.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the WAIT and MLS bits in
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock falls while the RDRF bit is
(4) Reading the last byte is performed by reading the ICDRR register as well.
the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST
bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock.
Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the read
data is unnecessary because of showing slave address and R/W).
set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the
acknowledge signal which returns to master device before reading the ICDRR register reflects the
following transfer frame.
Slave Receive Operation
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16. Clock Synchronous Serial Interface
2
C Bus Interface Mode).