MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 993
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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16.5.6.3
The nine DWords in this area represent a transaction working space for the host controller. The general
operational model is that the host controller can detect whether the overlay area contains a description of
an active transfer. If it does not contain an active transfer, then it follows the queue head horizontal link
pointer to the next queue head. The host controller will never follow the next transfer queue element or
alternate queue element pointers unless it is actively attempting to advance the queue. For the duration of
the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the
transfer is complete, the results are written back to the original queue element.
The DWord3 of a queue head contains a pointer to the source qTD currently associated with the overlay.
The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is
complete.
The DWords 4–11 of a queue head are the transaction overlay area. This area has the same base structure
as a queue element transfer descriptor. The queue head utilizes the reserved fields of the page pointers to
implement tracking the state of split transactions.
This area is characterized as an overlay because when the queue is advanced to the next queue element,
the source queue element is merged onto this area. This area serves an execution cache for the transfer.
Freescale Semiconductor
15–8
31–5
Bits
Bits
7–0
4–0
µFrame C-mask This field is ignored by the host controller unless the EPS field indicates this device is a low- or
µFrame S-mask Interrupt schedule mask. This field is used for all endpoint speeds. Software should set this field to
Current qTD
Pointer
Name
Name
—
Transfer Overlay
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-59. Endpoint Capabilities: Queue Head DWord 2 (continued)
Current element transaction descriptor link pointer. This field contains the address Of the current
transaction being processed in this queue and corresponds to memory address signals [31:5],
respectively.
Reserved, should be cleared. These bits are ignored by the host controller when using the value as
an address to write data. The actual value may vary depending on the usage.
full-speed device and this queue head is in the periodic list. This field (along with the Active and
SplitX-state fields) is used to determine during which micro-frames the host controller should
execute a complete-split transaction. When the criteria for using this field are met, a zero value in
this field has undefined behavior. This field is used by the host controller to match against the three
low-order bits of the FRINDEX register. If the FRINDEX register bits decode to a position where the
µFrame C- mask field is a one, then this queue head is a candidate for transaction execution. There
may be more than one bit in this mask set.
a zero when the queue head is on the asynchronous schedule. A non-zero value in this field
indicates an interrupt endpoint. The host controller uses the value of the three low-order bits of the
FRINDEX register as an index into a bit position in this bit vector. If the µFrame S-mask field has a
one at the indexed bit position then this queue head is a candidate for transaction execution. If the
EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is
determined by the PID_Code field contained in the execution area. This field is also used to support
split transaction types: Interrupt (IN/OUT). This condition is true when this field is non-zero and the
EPS field indicates this is either a full- or low-speed device. A zero value in this field, in combination
with existing in the periodic frame list has undefined results.
Table 16-60. Current qTD Link Pointer
Description
Description
Universal Serial Bus Interface
16-65
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