MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1071

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

software is required to track all transfer descriptors since pointers will no longer exist within the queue
head once the dTD is retired (see section Software Link Pointers).
In addition to the current and next pointers and the dTD overlay examined in section Operational Model
For Packet Transfers, the dQH also contains the following parameters for the associated endpoint:
Multipler, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including
these fields is demonstrated in the next section.
16.8.4.1
One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue
head:
16.8.4.2
As discussed in
treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a
setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated
here:
Freescale Semiconductor
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1. Copy setup buffer contents from dQH - RX to software buffer.
2. Acknowledge setup backup by writing a ‘1’ to the corresponding bit in ENDPTSETUPSTAT.
3. Check for pending data or status dTD’s from previous control transfers and flush if any exist as
Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol.
Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the
multiplier to 1, 2, or 3 as required bandwidth an in conjunction with the USB Chapter 9 protocol.
Note that in FS mode, the multiplier field can only be 1 for ISO endpoints.
Write the next dTD Terminate bit field to ‘1.’
Write the Active bit in the status field to ‘0.’
Write the Halt bit in the status field to ‘0.’
discussed in section Flushing/De-priming an Endpoint.
Queue Head Initialization
Operational Model for Setup Transfers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The DCD must only modify dQH if the associated endpoint is not primed
and there are no outstanding dTDs.
The acknowledge must occur before continuing to process the setup packet.
After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH - RX. Only the local software copy should be
examined.
Section 16.8.3.5, “Control Endpoint Operation Model,”
NOTE
NOTE
NOTE
setup transfer requires special
Universal Serial Bus Interface
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