MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 502
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
10.4.2.3.4
The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge of the
bus clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with
LCSn (if XACS = 1 and ACS = 10 or ACS = 11). Accordingly, assertion of LOE can be delayed (along
with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding
with LCSn negation
10.4.2.3.5
Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose
some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank
is delayed by the number of clock cycles specified in
cycle. The final bus turnaround cycle is automatically inserted by the eLBC for reads, regardless of the
setting of OR
10-54
LBCTL
LCLK
LCS n
LALE
LCSy
LAD
LOE
Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
n
TA
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
A
[EHTR].
Output Enable (LOE) Timing
Extended Hold Time on Read Accesses
Address 1
Latched Address 1
Read Data 1
Bus turnaround
Table 10-7
Address 2
in addition to any existing bus turnaround
Latched Address 2
Freescale Semiconductor
Data 2
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