MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 273

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.7.7
5.7.7.1
5.7.7.1.1
The following initialization sequence of GTM is recommended:
5.8
The device provides a power management control (PMC) unit, which enables the device to smoothly enter
and exit low power modes. Low power modes may be used when internal units in the device temporarily
or permanently do not perform any action.
The device uses one or more of the following methods for power saving:
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Write to GTCFRn in order to reset, to stop or to configure the appropriate timer’s operation:
cascaded timers configuration, gate mode configuration.
Write to GTPSRn[PPS] fields in order to program the appropriate timer’s clock primary prescaler.
Write to GTMDRn in order to choose an input clock, to program the secondary prescaler and to set
a desirable appropriate timer’s operational mode.
Clear GTEVRn[REF] and GTEVRn[CAP] by writing 1s in order to clear the previous events.
Write to GTRFR and to GTCNRn according to appropriate timer’s GTMDRn programming.
Write to GTCFRn[STPn] and to GTCFRn[RSTn] in order to initialize the appropriate timer’s
operation.
Dynamic power management
Shutting down unused blocks
Software-controlled power-down states
Low power state, which is reached by powering down the e300 and other non-essential blocks
(DDR controller, eLBC). This mode utilizes an on-chip split power supply allowing power to be
removed from a portion of the device.
Support for the PCI Power Management Interface Specification in both host and agent modes.
When the device is in either mode, the PMC is capable of placing the device into one of the
supported low-power states and supporting the power management event (PME) signaling
protocol.
Power Management Control (PMC)
Initialization/Application Information
Programming Guidelines
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
GTM Registers
Erratic behavior may occur if GTCFRn and GTPSR are not initialized before
the GTMDR. Only GTCFRn[RSTn] can be modified at any time
A write cycle to a GTCNRn[CNV] fields sets the register to the written
value, causing its corresponding primary and secondary prescalers,
(GTPSRn[PPS] and GTMDRn[SPS]), to be reset.
NOTE
NOTE
System Configuration
5-65