MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1115
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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[UDMB||UDLB:0b0000] = platform clock frequency/desired baud rate. Baud rates that can be generated
by specific input clock frequencies are shown in
Figure 18-4
Table 18-6
Figure 18-5
Table 18-7
Table 18-8
Freescale Semiconductor
Bits
Bits
0–7
0–7
UDMB Divisor most significant byte
Name
Name
UDLB Divisor least significant byte. This is concatenated with UDMB.
describes the UDMB.
describes the UDLB.
shows baud rate for a variety of input clock frequencies.
shows the bits in the UDMBs.
shows the bits in the UDLBs.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 18-4. Divisor Most Significant Byte Registers (UDMB1 and UDMB2)
Figure 18-5. Divisor Least Significant Byte Registers (UDLB1 and UDLB2)
Offset: 0x0_4501, 0x0_4601
Offset: 0x0_4500, 0x0_4600
Baud Rate
Reset
Reset
(Decimal)
128,000
19,200
38,400
56,000
9,600
W
W
R
R
0
0
Table 18-6. UDMB Field Descriptions
Table 18-7. UDLB Field Descriptions
Decimal
Table 18-8. Baud Rate Examples
866
433
216
148
65
Divisor
Table
Hex
1B1
362
D8
94
41
All zeros
All zeros
UDMB
UDLB
Description
Description
18-8.
(System Clock)
Input Clock
Frequency
(MHz)
133
133
133
133
133
Access: User read/write
Access: User read/write
Percent Error
(Decimal)
0.013
0.013
0.218
0.300
0.090
7
7
DUART
18-7
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