MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1113
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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18.3.1
The following sections describe the UART1 and UART2 registers.
18.3.1.1
These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when
read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY]
description.
Freescale Semiconductor
0x0_4501
0x0_4502
0x0_4503
0x0_4504
0x0_4505
0x0_4506
0x0_4507
0x0_4510
0x0_4600
0x0_4601
0x0_4602
0x0_4603
0x0_4604
0x0_4605
0x0_4606
0x0_4607
0x0_4610
Offset
Register Descriptions
UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART1 divisor most significant byte register
UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
UAFR—ULCR[DLAB] = 1 UART1 alternate function register
ULCR—ULCR[DLAB] = x UART1 line control register
UMCR—ULCR[DLAB] = x UART1 MODEM control register
ULSR—ULCR[DLAB] = x UART1 line status register
UMSR—ULCR[DLAB] = x UART1 MODEM status register
USCR—ULCR[DLAB] = x UART1 scratch register
UDSR—ULCR[DLAB] = x UART1 DMA status register
URBR—ULCR[DLAB] = 0 UART2 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART2 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART2 divisor least significant byte register
UIER—ULCR[DLAB] = 0 UART2 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART2 divisor most significant byte register
UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART2 FIFO control register
UAFR—ULCR[DLAB] = 1 UART2 alternate function register
ULCR—ULCR[DLAB] = x UART2 line control register
UMCR—ULCR[DLAB] = x UART2 MODEM control register
ULSR—ULCR[DLAB] = x UART2 line status register
UMSR—ULCR[DLAB] = x UART2 MODEM status register
USCR—ULCR[DLAB] = x UART2 scratch register
UDSR—ULCR[DLAB] = x UART2 DMA status register
Receiver Buffer Registers (URBR1 and URBR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 18-3. DUART Register Summary (continued)
Register
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
R
R
R
R
R
R
R
R
R
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x60
0x00
0x00
0x01
18.3.1.12/18-16
18.3.1.10/18-15
18.3.1.11/18-16
18.3.1.13/18-17
18.3.1.12/18-16
18.3.1.10/18-15
18.3.1.11/18-16
18.3.1.13/18-17
18.3.1.6/18-10
18.3.1.7/18-11
18.3.1.8/18-13
18.3.1.9/18-14
18.3.1.6/18-10
18.3.1.7/18-11
18.3.1.8/18-13
18.3.1.9/18-14
Section/Page
18.3.1.4/18-8
18.3.1.3/18-6
18.3.1.5/18-9
18.3.1.1/18-5
18.3.1.2/18-6
18.3.1.3/18-6
18.3.1.4/18-8
18.3.1.3/18-6
18.3.1.5/18-9
DUART
18-5
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