MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 811
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.5.3.6.28 Transmit Broadcast Packet Counter (TBCA)
Figure 15-79
Table 15-83
15.5.3.6.29 Transmit Pause Control Frame Counter (TXPF)
Figure 15-80
Table 15-84
Freescale Semiconductor
16–31
10–31
0–15
Bits
Bits
0–9
Offset eTSEC1:0x2_46EC; eTSEC2:0x2_56EC
Reset
Offset eTSEC1:0x2_46F0; eTSEC2:0x2_56F0
Reset
W
W
R
R
Name
TXPF
Name
TBCA
0
0
—
—
describes the fields of the TBCA register.
describes the fields of the TXPF register.
describes the definition for the TBCA register.
describes the definition for the TXPF register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
transmitted with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is
Figure 15-80. Transmit Pause Control Frame Counter Register Definition
Reserved
Transmit broadcast packet counter. Increments for each broadcast frame transmitted (excluding multicast
frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Figure 15-79. Transmit Broadcast Packet Counter Register Definition
—
—
Table 15-83. TBCA Field Descriptions
Table 15-84. TXPF Field Descriptions
9
10
All zeros
All zeros
15 16
Description
Description
TBCA
Enhanced Three-Speed Ethernet Controllers
TXPF
Access: Read/Write
Access: Read/Write
15-93
31
31
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