MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 765
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.5.3.2.11 Transmit Timestamp Identification Register (TMR_TXTS1–2_ID)
Transmit timestamp identification register (TMR_TXTSn_ID). This register holds the identification
number of the transmitted frame corresponding to the timestamp captured in TMR_TXTSn_H/L. Each
time the eTSEC is instructed to capture the timestamp of an outgoing frame via TxFCB[PTP] the
associated field in TxFCB[PTP_ID] is stored in this register, overwriting the previous value.
This register is read only in normal operation.
TMR_TXTSn_ID register.
Table 15-25
15.5.3.2.12 Transmit Timestamp Register (TMR_TXTS1–2_H/L)
Transmit stamp register (TMR_TXTSn_H/L). This register holds the value of the TMR_CNT_H/L when
a frame tagged for timestamp capture (via Tx FCB[PTP]) is transmitted. Upon transmission of the start of
frame symbol of such a frame, the value in TMR_CNT_H/L is copied into TMR_TXTSn_H/L.
This register is read only in normal operation.
Offset eTSEC1:0x2_42C0+8×n; eTSEC2:0x2_52C0+8×n
Table 15-26
Freescale Semiconductor
Reset
Offset eTSEC1:0x2_4280+4×n; eTSEC2:0x2_5280+4×n
Reset
16–31
0–15
0–63
Bits
Bits
W
W
R
R
0
0
TXTS_H/L
TXTS_ID
Name
Name
describes the fields of the TMR_TXTSn_ID register.
describes the fields of the TMR_TXTSn_H/L register.
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Tx timestamp identification field
Timestamp field of the transmitted PTP packet’s start of frame detection.
Table 15-26. TMR_TXTS n _H/L Register Field Descriptions
Table 15-25. TMR_TXTS n _ID Register Field Descriptions
TXTS_H
Figure 15-21. TMR_TXTS n _H/L Register Definition
Figure 15-20. TMR_TXTS n _ID Register Definition
—
Figure 15-20
Figure 15-21
All zeros
All zeros
31 32
15 16
Description
Description
describes the definition for the
depicts TMR_TXTSn_H/L.
Enhanced Three-Speed Ethernet Controllers
TXTS_ID
TXTS_L
Access: Read only
Access: Read only
15-47
31
63
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