MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 842

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.4.3.1
Figure 15-117
Table 15-126
15-124
Offset 0x00
Reset
Bits
4–5
0
1
2
3
6
7
8
W
R PHY
Reset
PHY Reset PHY reset. This bit is cleared by default. This bit is self-clearing.
Reset AN Reset auto-negotiation. This bit is cleared by default and is self-clearing.
1
Speed[0] Speed selection. This bit defaults to a cleared state and should always be cleared, which corresponds to
0
0
Enable
Duplex
Name
R = Read-only, WO = Write Only, R/W = Read and Write, LH = Latches High, LL = Latches Low,
SC = Self-clearing,
Full
AN
Address
—
—
—
Offset
0x0F
0x08
0x10
0x11
— Speed[0] AN Enable
0
1
describes the fields of the CR register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the CR register.
Control Register (CR)
0 Normal operation.
1 The internal state of the TBI is reset. This in turn may change the state of the TBI link partner.
Reserved
1000 Mbps speed.Setting this field controls the speed at which the TBI operates. The table for Speed[1]
provides the appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Auto-negotiation enable. This bit is set by default.
0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.
1 Auto-negotiation process enabled.
Reserved
0 Normal operation.
1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled.
Duplex mode. This bit is set by default.
0 Reserved.
1 Full-duplex operation.
Reserved, should be cleared.
0
2
AN link partner ability next page
(ANLPANP)
Extended status (EXST)
Jitter diagnostics (JD)
TBI control (TBICON)
3
1
Table 15-125. TBI MII Register Set (continued)
Figure 15-117. Control Register Definition
Table 15-126. CR Field Descriptions
0
4
Name
—
0
5
Reset AN Full Duplex — Speed[1]
0
6
Description
1
7
Access
R/W
R/W
R
R
8
0
1
9
16 bits
16 bits
16 bits
16 bits
Size
10
0
15.5.4.3.10/15-133
0
15.5.4.3.7/15-130
15.5.4.3.8/15-131
15.5.4.3.9/15-132
Section/page
Freescale Semiconductor
0
Access: Read/Write
—
0
0
15
0