MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 370

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Integrated Programmable Interrupt Controller (IPIC)

SIPNR_L is shown in

and SIMSR_L.

INT n Each implemented bit (listed in

lists implemented SIPNR_L fields. Note that these field assignments are also valid for SIFCR_L

defines the bit fields of SIPNR_H.

received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the

user clears the SIPNR bit by clearing the corresponding event register bit.

SIPNR bits are read only. Writing to this register has no effect.

Note that the SIPNR bit positions are not changed according to their relative priority.

For unimplemented bits, writes are ignored, read = 0.

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments (continued)

Figure 8-5. System Internal Interrupt Pending Register (SIPNR_L)

Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments

Table 8-8. SIPNR_H Field Descriptions

n (Implemented bits are listed in

8-7) corresponds to an internal interrupt source. When an interrupt is

eTSEC1 1588 timer

eTSEC2 1588 timer

Freescale Semiconductor

Access: Read only