MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 538

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Enhanced Local Bus Controller

In case a system contains a memory hierarchy with high speed synchronous memories (synchronous

SRAM) and lower speed asynchronous memories (for example, FLASH EPROM and peripherals) the

GPCM-controlled memories should be decoupled by buffers to reduce capacitive loading on the bus.

Those buffers have to be taken into account for the timing calculations.

To calculate address setup timing for a slower peripheral/memory device, several parameters have to be

added: propagation delay for the address latch, propagation delay for the buffer and the address setup for

the actual peripheral. Typical values for the two propagation delays are in the order of 3–6 ns, so for a

133-MHz bus frequency, LCS should arrive on the order of 3 bus clocks later.

For data timings, only the propagation delay of one buffer plus the actual data setup time has to be

Local Bus Interface

GPCM Timings

Local Bus Interface

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Figure 10-71. Local Bus Peripheral Hierarchy for High Bus Speeds

Figure 10-72. GPCM Address Timings

Muxed Address/Data

Unmuxed Address

Buffered Data

Muxed Address/Data

Unmuxed Address

Buffered Address

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