MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 514

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Enhanced Local Bus Controller

The FCM command (CM0–CM3, CW0, CW1), address (CA, PA, UA), and data write (WB, WS)

instructions all share the same basic timing attributes. Assertion of LFWE initiates transfer via LAD[0:7],

and the options in ORn for FCM mode establish the set-up, hold, and wait state timings with respect to

LFWE, as shown in

The timing parameters are summarized in

Option Register Attributes

In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

FCM Command, Address, and Write Data Timing

Table 10-36. FCM Command, Address, and Write Data Timing Parameters

Figure 10-51. Timing of FCM Command/Address and Write Data Cycles

(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)

= Command/address to write data delay.

= Command to LFWE set-up time.

= Command to LFWE hold time.

command/address

write cycle #1

Timing Parameter (LCLK Clock Cycles)

= LFWE pulse time, driven low.

= Command wait state time.

= Command cycle time.

write cycle #2

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