MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 514
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
10.4.3.3.2
The FCM command (CM0–CM3, CW0, CW1), address (CA, PA, UA), and data write (WB, WS)
instructions all share the same basic timing attributes. Assertion of LFWE initiates transfer via LAD[0:7],
and the options in ORn for FCM mode establish the set-up, hold, and wait state timings with respect to
LFWE, as shown in
The timing parameters are summarized in
10-66
1
Option Register Attributes
LCLK
(unused)
LFCLE/
LFALE
LFWE
LAD[0:7]
TA
TRLX
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
0
0
0
0
1
1
1
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FCM Command, Address, and Write Data Timing
Table 10-36. FCM Command, Address, and Write Data Timing Parameters
Notes:
Figure 10-51. Timing of FCM Command/Address and Write Data Cycles
CHT
0
0
1
1
0
0
1
1
Figure
t
t
t
CST
CHT
ADL
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)
CST
10-51.
= Command/address to write data delay.
0
1
0
1
0
1
0
1
= Command to LFWE set-up time.
= Command to LFWE hold time.
command/address
t
write cycle #1
CST
t
t
WP
t
WC
WS
t
CST
¼
¼
½
½
0
0
1
1
Table
t
Timing Parameter (LCLK Clock Cycles)
CHT
1½
1½
½
½
1
1
2
2
10-36.
t
t
CHT
ADL
2×SCY
2×SCY
2×SCY
2×SCY
SCY
SCY
SCY
SCY
t
WS
t
t
t
WP
WS
WC
½+2×SCY
½+2×SCY
1+2×SCY
= LFWE pulse time, driven low.
= Command wait state time.
= Command cycle time.
1½+SCY
1¼+SCY
¾+SCY
1+SCY
2×SCY
t
WP
write cycle #2
3+2×SCY
3+2×SCY
3+2×SCY
3+2×SCY
write data
2+SCY
2+SCY
2+SCY
2+SCY
t
WC
1
Freescale Semiconductor
4×(2+SCY)
4×(2+SCY)
4×(2+SCY)
4×(2+SCY)
8×(2+SCY)
8×(2+SCY)
8×(2+SCY)
8×(2+SCY)
t
ADL
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