MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 275

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.8.2.1
The power management controller configuration register (PMCCR), shown in
whether only the PowerPC core will enter low power state upon quiesce request or additional parts of the
device will also enter low power state.
Table 5-5
Freescale Semiconductor
Offset 0x00B00
Reset
0–29
‘
Bits
30
31
W
R
0
DLPEN
SLPEN
Name
defines the bit fields of PMCCR.
—
Power Management Controller Configuration Register (PMCCR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved. Write has no effect, read returns 0.
DDR SDRAM low power enable
0 The DDR SDRAM memory controller is prevented from entering low power state.
1 The DDR SDRAM memory controller will enter low power state when the rest of the system enters low
System low power enable
0 The system is prevented from entering low power state.
1 The system will enter low power state when a quiesce request from the PowerPC core arrives. This bit
power, according to SLPEN setting. DDR SDRAM will enter self-refresh mode (if enabled by
DDR_SDRAM_CFG[SREN] memory controller register) and DDR clocks (MCK n ) are shut off. This bit is
cleared when the device exits from low power state. Note that setting this bit without setting SLPEN has
no effect.
is cleared when the device exits from low power state.
Figure 5-51. Power Management Controller Configuration Register
Table 5-67. PMCCR Bit Settings
—
All zeros
Description
Figure
29
5-51, controls
System Configuration
Access: Read/Write
DLPEN SLPEN
30
31
5-67