MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 495

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

The basic GPCM write timing parameters that may be set by the ORn attributes are shown in

The write access cycle commences upon latching of the memory address (LALE negated), and concludes

when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data

Freescale Semiconductor

Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.

Option Register Attributes

GPCM Write Signal Timing

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Table 10-32. GPCM Read Control Signal Timing

Signal Timing (LCLK clock cycles)

Enhanced Local Bus Controller