MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 35
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Paragraph
Number
17.4.4.2.1
17.4.4.2.2
17.4.4.3
17.4.5
17.4.5.1
17.4.5.2
17.4.5.3
17.4.5.4
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.5.6
17.5.7
17.5.8
17.5.8.1
17.5.8.2
18.1
18.1.1
18.1.2
18.2
18.2.1
18.2.2
18.3
18.3.1
18.3.1.1
18.3.1.2
18.3.1.3
18.3.1.4
18.3.1.5
18.3.1.6
18.3.1.7
18.3.1.8
18.3.1.9
18.3.1.10
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Initialization/Application Information ......................................................................... 17-19
Overview........................................................................................................................ 18-1
External Signal Descriptions ......................................................................................... 18-3
Memory Map/Register Definition ................................................................................. 18-4
Boot Sequencer Mode.............................................................................................. 17-15
Interrupt Service Routine Flowchart........................................................................ 17-19
Initialization Sequence............................................................................................. 17-21
Generation of START .............................................................................................. 17-21
Post-Transfer Software Response ............................................................................ 17-21
Generation of STOP................................................................................................. 17-22
Generation of Repeated START .............................................................................. 17-22
Generation of SCLn When SDAn is Negated ......................................................... 17-22
Slave Mode Interrupt Service Routine..................................................................... 17-22
Features...................................................................................................................... 18-2
Modes of Operation ................................................................................................... 18-3
Signal Overview ........................................................................................................ 18-3
Detailed Signal Descriptions ..................................................................................... 18-3
Register Descriptions................................................................................................. 18-5
Clock Stretching .................................................................................................. 17-15
Using the Boot Sequencer for Reset Configuration ............................................ 17-16
EEPROM Calling Address .................................................................................. 17-16
EEPROM Data Format ........................................................................................ 17-16
Boot Sequencer Done Indication ......................................................................... 17-19
Slave Transmitter and Received Acknowledge ................................................... 17-23
Loss of Arbitration and Forcing of Slave Mode.................................................. 17-23
Receiver Buffer Registers (URBR1 and URBR2)................................................. 18-5
Transmitter Holding Registers (UTHR1 and UTHR2).......................................... 18-6
Divisor Most and Least Significant Byte Registers (UDMB and UDLB) ............ 18-6
Interrupt Enable Registers (UIER1 and UIER2) ................................................... 18-8
Interrupt ID Registers (UIIR1 and UIIR2) ............................................................ 18-9
FIFO Control Registers (UFCR1 and UFCR2) ................................................... 18-10
Line Control Registers (ULCR1 and ULCR2) .................................................... 18-11
MODEM Control Registers (UMCR1 and UMCR2).......................................... 18-13
Line Status Registers (ULSR1 and ULSR2) ....................................................... 18-14
MODEM Status Registers (UMSR1 and UMSR2) ............................................. 18-15
Input Signal Synchronization .......................................................................... 17-15
Filtering of SCLn and SDAn Lines ................................................................. 17-15
Contents
Chapter 18
DUART
Title
Number
Page
xxxv
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