MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 241

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 5-35
5.4.4.3
The system watchdog service register (SWSRR) is shown in
enabled, a write of 0x556C followed by a write 0xAA39 to the SWSRR register before the watchdog
counter times out prevents a device reset. If the SWSRR register is not serviced before the timeout, a signal
from the watchdog timer to the reset or interrupt controller module asserts a system reset or interrupt
(depending on the setting of SWCRR[SWRI]).
Both writes must occur before the timeout in the order listed, but any number of instructions can be
executed between the two writes. However, writing any value other than 0x556C or 0xAA39 to the
SWSRR register resets the servicing sequence, requiring both values to be written to keep the watchdog
timer from causing a reset. Reset initializes the SWSRR[WS] field to 0x0000. SWSRR can be written at
any time, but returns all zeros when read.
Table 5-36
Freescale Semiconductor
16–31
0–15
0–15
Bits
Bits
Offset 0xE
Reset
W
R
SWCN Software watchdog count field. The read-only SWCNR[SWCN] field reflects the current value in the watchdog
Name
Name
WS
—
0
defines the bit fields of SWCNR.
defines the bit fields of SWCNR.
System Watchdog Service Register (SWSRR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
counter. Writing to the SWCNR register has no effect, and write cycles are terminated normally. Reset
initializes the SWCNR[SWCN] field to 0xFFFF.
Note: Reading the 16 least-significant bits of 32-bit SWCNR register with two 8-bit reads is not guaranteed
Software watchdog service field.
The user should periodically write 0x556C followed by 0xAA39 to this register to prevent a software watchdog
timer timeout. SWSRR[WS] can be written at any time, but returns all zeros when read.
to return a coherent value.
Figure 5-21. System Watchdog Service Register (SWSRR)
Table 5-35. SWCNR Bit Settings
Table 5-36. SWSRR Bit Settings
All zeros
Description
Description
WS
Figure
5-21. When the watchdog timer is
System Configuration
Access: Write only
5-33
15