MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 541
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 10-43
10.5.4
In order to program the eLBC and FCM for executing NAND Flash command sequences, command codes
and pause states should be obtained from the relevant NAND Flash device data sheet and programmed into
FCM configuration registers. This section illustrates some common sequences for large-page,
multi-gigabit NAND Flash EEPROMs; however, details should be verified against manufacturers’
specific programming data.
Throughout these examples it is assumed that one or more banks of eLBC has been configured under FCM
control (BRn[MSEL] = 001), with base address, port size, ECC mode, and timing parameters configured
in accordance with the device’s hardware specifications.
Freescale Semiconductor
1
Command Sequence Examples for NAND Flash EEPROM
lists the bytes required on the data bus for read cycles.
Address state is the calculated address for port size.
Half Word
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transfer
Word
Size
Byte
Table 10-43. Data Bus Drive Requirements For Read Cycles
Address
State
3 lsbs
000
001
010
011
100
101
110
111
000
001
010
100
101
110
000
100
1
OP0
OP2
OP4
OP6
OP0
OP2
OP4
OP6
OP0
OP4
0–7
—
—
—
—
—
—
8–15
OP1
OP3
OP5
OP7
OP1
OP1
OP3
OP5
OP5
OP7
OP1
OP5
—
—
—
—
16-Bit
Port Size/LAD Data Bus Assignments
16–23
24–31
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
OP0
OP1
OP2
OP4
OP5
OP6
OP0
OP4
0–7
8–15
8-Bit
16–23
Enhanced Local Bus Controller
24–31
10-93
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