MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 285

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

The relationship between the e300 core and the defined PMC power states is illustrated in

Freescale Semiconductor

Generating or responding to appropriate control signals relative to low power modes: VDD

switching control (EXT_PWR_CTRL) output signal and input signal indicating external power is

stable (PMC_PWR_OK)

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

The relationships shown below between e300 core doze, nap, and sleep

modes and PCI D-states are only suggested. There is no forced hardware

relationship between these states. For example, if a PCI host sets

PCIPMR1[Power_State] = 01, it is still up to the software running on the

e300 to put itself into doze mode.

Table 5-74. Software-Controller Power-Down States—Basic Description

PCI D- state

All units operating normally

Core stops dispatching new instructions

(core is halted), and most of the core

functional units are disabled. System

operates normally.

Core is stopped with its clocks off except to

time base. System operates normally.

Core is stopped with its clocks off. Core

clocks powered down to all blocks (including

core time base) except to the

interrupt unit. System operates normally.

Snoop Interrupt

Core Responds

System Configuration