MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1127

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

18.4.1
The UART bus is a serial, full-duplex, point-to-point bus as shown in
devices are attached to the same signals and there is no need for address or arbitration bus cycles.
A standard UART bus transfer is composed of either three or four parts:
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on
SOUT.
The following sections describe the four components of the serial interface, the baud-rate generator, local
loopback mode, different errors, and FIFO mode.
18.4.1.1
A write to UTHR generates a START bit on the SOUT signal.
defined as a logic 0. The START bit denotes the beginning of a new data transfer which is limited to the
bit length programmed in ULCR.When the bus is idle, SOUT is high.
18.4.1.2
Each data transfer contains 5, 6, 7, or 8 bits of data. The ULCR data bit length for the transmitter and
receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur.
A transfer begins when UTHR is written. At that time, a START bit is generated followed by 5 to 8 of the
data bits previously written to the UTHR. The data bits are driven from the least- to the most-significant
bits. After the parity and STOP bits, a new data transfer can begin if new data is written to UTHR.
18.4.1.3
The user has the option of using even, odd, no parity, or stick parity (see
Registers (ULCR1 and ULCR2).”
Freescale Semiconductor
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•
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SOUT1
rxcnt
START bit
Data transfer (least significant bit is first data bit on the bus)
Parity bit (optional)
STOP bits
START
Serial Interface
START Bit
Data Transfer
Parity Bit
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
D6 D5 D4 D3 D2 D1 D0 PTY
1
2
Variable Data Bits
Figure 18-16. UART Bus Interface Transaction Protocol Example
Two 7-Bit Data Transmissions with Parity and 2-Bit STOP Transactions
3
4
5
Both the receiver and transmitter parity definitions must agree before
6
Even/Odd Parity
7
Optional
8
STOP Bits
9
10
D6 D5 D4 D3 D2 D1 D0 PTY
1
Figure 18-16
2
3
Figure
Data Bits
4
Section 18.3.1.7, “Line Control
5
shows that the START bit is
18-16. Therefore, only two
6
7
8
STOP Bits
9
10
DUART
18-19