MPC8313E-RDBB Freescale Semiconductor, MPC8313E-RDBB Datasheet
MPC8313E-RDBB
Specifications of MPC8313E-RDBB
Related parts for MPC8313E-RDBB
MPC8313E-RDBB Summary of contents
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... Freescale Semiconductor Technical Data MPC8313E PowerQUICC Hardware Specifications This document provides an overview of the MPC8313E PowerQUICC™ II Pro processor features, including a block diagram showing the major functional components. The MPC8313E is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several ...
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... Overview 1 Overview The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role controller and an on-chip full-speed PHY, a programmable interrupt controller, dual I 4-channel DMA controller, and a general-purpose I/O port ...
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... Serial Interfaces The following interfaces are supported in the MPC8313E: dual UART, dual I 1.3 Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i®, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are as follows: • ...
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... Overview 1.6 USB Dual-Role Controller The MPC8313E USB controller includes the following features: • Supports USB on-the-go mode, which includes both device and host functionality, when using an external ULPI (UTMI + low-pin interface) PHY • Compatible with Universal Serial Bus Specification, Rev. 2.0 • ...
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... The PIC programming model supports 5 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. 1.9 Power Management Controller (PMC) The MPC8313E power management controller includes the following features: • Provides power management when the device is used in both host and agent modes • ...
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... The 16-byte FIFOs are supported for both the transmitter and the receiver. The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices ...
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... MPC8313E. Note that the values in Table 2 are the recommended and tested operating conditions particular block is given a voltage falling within the range in the Recommended Value column, the MPC8313E is capable of delivering the MPC8313E PowerQUICC Freescale Semiconductor Table 1 ...
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... and V must track each other and must vary in the same direction—either in the positive or negative direction. 2 Some GPIO pins may operate from a 2.5-V supply when configured for other functions. MPC8313E PowerQUICC 8 Recommended Symbol Value V 1.0 V ± 1.0 V ± DDC XCOREV 1.0 ...
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... Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8313E. G/L/NV DD G/L/NV DD G/L/ Note: 1. Note that t interface interface. Figure 2. Overshoot/Undershoot Voltage for GV 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. Driver Type Local bus interface utilities signals ...
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... I/O supplies reach 0.7 V; see (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies ( and not have any ordering requirements with respect to one another ...
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... RGMII, 125 MHz USBDR controller load = MHz Other I/O Table 6 shows the estimated core power dissipation of the MPC8313E while transitioning into the D3 warm low-power state. Table 6. MPC8313E Low-Power Modes Power Dissipation 333-MHz Core, 167-MHz CSB D3 warm 1 All interfaces are enabled. For further power savings, disable the clocks to unused blocks ...
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... PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E. Table 8. SYS_CLK_IN AC Timing Specifications ...
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... RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8313E. 5.1 RESET DC Electrical Characteristics Table 9 provides the DC electrical characteristics for the RESET pins. Table 9. RESET Pins DC Electrical Characteristics Characteristic Input high voltage ...
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... It is the supply to which far end signal termination is made and is expected equal This rail should track variations in the DC level of MV REF 4. Output leakage is measured with all outputs disabled MPC8313E PowerQUICC 14 Min 1 Table 11. PLL Lock Times Min — ...
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... REF 4. Output leakage is measured with all outputs disabled Table 15 provides the DDR capacitance when Table 15. DDR SDRAM Capacitance for GV Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled MPC8313E PowerQUICC Freescale Semiconductor 1 (typ Symbol DIO = 1.8 V ± 0.090 MHz 25° ...
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... MDQS and any corresponding bit that CISKEW is captured with MDQS This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation absolute value of t CISKEW MPC8313E PowerQUICC 16 . REF Symbol Min I — ...
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... ADDR/CMD output hold with respect to MCK MCS output setup with respect to MCK MCS output hold with respect to MCK MCK to MDQS Skew MDQ//MDM output setup with respect to MDQS MDQ//MDM output hold with respect to MDQS MDQS preamble start MPC8313E PowerQUICC Freescale Semiconductor t MCK DISKEW ...
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... CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. ...
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... CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. ...
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... DC electrical characteristics for the DUART interface. Table 22. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage –100 μA High-level output voltage 100 μA Low-level output voltage Input current (0 V ≤V ≤ MPC8313E PowerQUICC 20 t MCK t ,t DDKHAS DDKHCS DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH ...
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... JEDEC EIA/JESD8-5. Parameter Symbol Supply voltage 3 /LV DDA DDB Output high voltage V OH MPC8313E PowerQUICC Freescale Semiconductor Table 23. DUART AC Timing Specifications th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Table 24. MII DC Electrical Characteristics Conditions — –4 ...
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... LV IN 8.2 MII, RGMII, and RTBI AC Timing Specifications The AC timing specifications for MII, RMII, RGMII, and RTBI are presented in this section. 8.2.1 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8313E PowerQUICC 22 Conditions Min ...
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... MII receive AC timing specifications. Table 27. MII Receive AC Timing Specifications At recommended operating conditions with LV Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK MPC8313E PowerQUICC Freescale Semiconductor / LV /NV of 3.3 V ± 0.3 V. DDA DDB ...
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... R (rise (fall). Figure 9 provides the AC test load for TSEC. Output Figure 10 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER Figure 10. MII Receive AC Timing Diagram RMII AC Timing Specifications MPC8313E PowerQUICC /NV of 3.3 V ± 0.3 V. DDA DDB DD 1 Symbol ...
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... Table 29. RMII Receive AC Timing Specifications At recommended operating conditions with NV Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise V (min (max MPC8313E PowerQUICC Freescale Semiconductor of 3.3 V ± 0 Symbol t RMX t t RMXH/ RMX ...
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... RGMII and RTBI AC timing specifications. Table 30. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T MPC8313E PowerQUICC 26 of 3.3 V ± 0 Symbol (min RMXF (first three letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8313E PowerQUICC Freescale Semiconductor /LV of 2.5 V ± 5%. DDA DDB 1 Symbol RGTH RGT t ...
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... SGMII Interface Electrical Characteristics Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes interface of MPC8313E as shown in Figure output pin of the SerDes transmitter differential pair features a 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XCOREVSS. The reference circuit of the SerDes transmitter and receiver is shown in When an eTSEC port is configured to operate in SGMII mode, the parallel interface’ ...
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... SerDes transmitter is terminated with 100-Ω differential load between TX and TX also referred to as output common mode voltage. OS Transmitter MPC8313E SGMII SerDes Interface Receiver Figure 15. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8313E PowerQUICC Freescale Semiconductor Symbol Min Typ 0.95 1 — ...
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... On-chip termination to XCOREV SS 8.3.4 SGMII AC Timing Specifications This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are measured at the transmitter outputs (TX[n] and TX[n the receiver inputs (RX[n] and RX[n]) as depicted in Figure MPC8313E PowerQUICC Ω 50 Ω 50 Ω 50 Ω ...
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... Each UI is 800 ps ± 100 ppm. 3. The external AC coupling capacitor is required recommended to be placed near the device transmitter outputs. 4. Refer to the RapidIO™ 1x/4x LP Serial Physical Layer Specification , for interpretation of jitter specifications. MPC8313E PowerQUICC Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management = 1.0 V ± ...
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... RX_DIFFp-p-max V /2 RX_DIFFp-p-min 0 – RX_DIFFp-p-min – RX_DIFFp-p-max Figure 17. SGMII Receiver Input Compliance Mask D+ Package D+ Package D– Package Figure 18. SGMII AC Test/Measurement Load MPC8313E PowerQUICC 32 0 0.275 0.4 Time (UI) Pin Pin Silicon + Package Ω Pin ™ II Pro Processor Hardware Specifications, Rev 0.6 0.725 Ω ...
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... At recommended operating conditions with L/TV Parameter/Condition TSEC_1588_CLK clock period TSEC_1588_CLK duty cycle TSEC_1588_CLK peak-to-peak jitter Rise time eTSEC_1588_CLK (20%–80%) Fall time eTSEC_1588_CLK (80%–20%) TSEC_1588_CLK_OUT clock period TSEC_1588_CLK_OUT duty cycle TSEC_1588_PULSE_OUT MPC8313E PowerQUICC Freescale Semiconductor t T1588CLKOUT t T1588CLKOUTH t T1588OV T1588CLKOUT t T1588CLK t T1588CLKH t T1588TRIGH Table 36 ...
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... RX_CLK PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers need least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers. 3. The maximum value of t ...
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... For rise and fall times, the latter MDC convention is used with the appropriate letter: R (rise (fall). 2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency of the Mgmt Clock EC_MDC.) MPC8313E PowerQUICC Freescale Semiconductor Conditions — – ...
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... A – B volts. This is also referred as each signal wire’s single-ended swing. 2. Differential output voltage, V The differential output voltage (or swing) of the transmitter, V the two complimentary output voltages: V negative. 3. Differential input voltage, V The differential input voltage (or swing) of the receiver, V complimentary input voltages: V MPC8313E PowerQUICC 36 t MDC t t MDCF MDCH ...
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... The differential output signal ranges between 500 and –500 mV, in other words, V differential voltage ( 500 mV. The peak-to-peak differential voltage (V DIFFp MPC8313E PowerQUICC Freescale Semiconductor DIFFp = |A – B| volts. DIFFp DIFFp × ...
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... If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to XCOREV DC exceeds the maximum input current limitations, then it must be SS AC-coupled off-chip. • The input amplitude requirement. This requirement is described in detail in the following sections. MPC8313E PowerQUICC 38 are specified in DD followed by on-chip AC coupling. SS ™ ...
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... Figure 23. Receiver of SerDes Reference Clocks 9.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8313E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • ...
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... LVPECL outputs can produce a signal with too large of an amplitude and may need to be DC-biased at the clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC coupling. MPC8313E PowerQUICC 40 400 mV < SD_REF_CLK Input Amplitude < 800 mV , the differential reference clocks inputs are HCSL SS ™ ...
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... MPC8313E SerDes reference clock receiver requirement provided in this document. Figure 27 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8313E SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω ...
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... R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8313E SerDes3 reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the LVPECL output’ ...
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... Figure 30 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 30. Single-Ended Connection (Reference Only) 9 ...
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... Refer to the following section for detailed information: • Section 8.3.2, “AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK” 9.2.4.1 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. MPC8313E PowerQUICC 1.0 V ± 5%. DD_SRDS1 DD_SRDS2 Symbol ...
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... USB DC Electrical Characteristics Table 41 provides the DC electrical characteristics for the USB interface. Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage MPC8313E PowerQUICC Freescale Semiconductor Table 41. USB DC Electrical Characteristics Symbol ...
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... USBDR_CLK Input Signals t USKHOV Output Signals 10.2 On-Chip USB PHY This section describes the DC and AC electrical specifications for the on-chip USB PHY of the MPC8313E. See Chapter 7 in the USB Specifications Rev. 2, for more information. MPC8313E PowerQUICC 46 1 Symbol Min t 15 USCK ...
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... High-level input voltage for Rev 2.x or later Low-level input voltage 1 Input current High-level output voltage, (LV = min Low-level output voltage, (LV = min Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned. MPC8313E PowerQUICC Freescale Semiconductor Symbol V V Conditions — — Symbol –2 mA) ...
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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 36 provides the AC test load for the local bus. Output MPC8313E PowerQUICC 48 1 Symbol t ...
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... Figure 37. Local Bus Signals, Non-Special Signals Only LCLK T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 38. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8313E PowerQUICC Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t ...
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... Figure 39. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV LCLK Input Signals: LAD[0:15] Input Signal: LGTA t LBKHOV Output Signals: LBCTL/LBCKE/LOE t LBKHOV Output Signals: LAD[0:15] t LALEHOV LALE Figure 40. Local Bus Signals, LALE with Respect to LCLK MPC8313E PowerQUICC 50 t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ t LBKHOV t LBIVKH t LBIVKH t ...
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... JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: Valid times: MPC8313E PowerQUICC Freescale Semiconductor Symbol Condition V — — ...
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... Figure 41. AC Test Load for the JTAG Interface Figure 42 provides the JTAG clock input timing diagram. JTAG External Clock Figure 42. JTAG Clock Input Timing Diagram Figure 43 provides the TRST timing diagram. TRST MPC8313E PowerQUICC 52 Table 2). 2 Symbol Boundary-scan data t JTKLDX TDO ...
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... Data Outputs Figure 45 provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 45. Test Access Port Timing Diagram MPC8313E PowerQUICC Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (NV DD Figure 44. Boundary-Scan Timing Diagram ...
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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines 13.2 ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...
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... PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8313E is configured as a host or agent device. Table 52 shows the PCI AC timing specifications at 66 MHz. ...
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... Input timings are measured at the pin. Figure 48 provides the AC test load for PCI. Output Figure 49 shows the PCI input AC timing conditions. CLK Input Figure 49. PCI Input AC Timing Measurement Conditions MPC8313E PowerQUICC Freescale Semiconductor 1 Symbol Min t — PCKHOV t 2 ...
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... Timers This section describes the DC and AC electrical specifications for the timers. 15.1 Timers DC Electrical Characteristics Table 54 provides the DC electrical characteristics for the MPC8313E timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 54. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...
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... Table 57. GPIO (When Operating at 2 Electrical Characteristics Parameters Symbol Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current MPC8313E PowerQUICC Freescale Semiconductor = 50 Ω Figure 51. Timers AC Test Load Symbol Condition –8.0 mA ...
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... This section describes the DC and AC electrical specifications for the external interrupt pins. 17.1 IPIC DC Electrical Characteristics Table 59 provides the DC electrical characteristics for the external interrupt pins. Characteristic Input high voltage Input low voltage Input current Output low voltage Output low voltage MPC8313E PowerQUICC 60 Conditions Ω Figure 52 ...
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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 18 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8313E. 18.1 SPI DC Electrical Characteristics Table 61 provides the DC electrical characteristics for the MPC8313E SPI ...
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... SPIMOSI (See Note) Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 54. SPI AC Timing in Slave Mode (External Clock) Diagram MPC8313E PowerQUICC 62 Table 62. SPI AC Timing Specifications Symbol t NEIXKH (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example, t ...
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... Note: The clock edge is selectable on SPI. Figure 55. SPI AC Timing in Master Mode (Internal Clock) Diagram 19 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in a thermally enhanced plastic ball grid array (TEPBGAII), see MPC8313E TEPBGAII,” ...
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... Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Package code 5368 is to account for PGE and the built-in heat spreader. Figure 56. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8313E TEPBGAII MPC8313E PowerQUICC 64 ™ ...
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... Pinout Listings Table 63 provides the pin-out listing for the MPC8313E, TEPBGAII package. Table 63. MPC8313E TEPBGAII Pinout Listing Signal MEMC_MDQ0 MEMC_MDQ1 MEMC_MDQ2 MEMC_MDQ3 MEMC_MDQ4 MEMC_MDQ5 MEMC_MDQ6 MEMC_MDQ7 MEMC_MDQ8 MEMC_MDQ9 MEMC_MDQ10 MEMC_MDQ11 MEMC_MDQ12 MEMC_MDQ13 MEMC_MDQ14 MEMC_MDQ15 MEMC_MDQ16 MEMC_MDQ17 MEMC_MDQ18 MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal MEMC_MDQ29 MEMC_MDQ30 MEMC_MDQ31 MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS0 MEMC_MDQS1 MEMC_MDQS2 MEMC_MDQS3 MEMC_MBA0 MEMC_MBA1 MEMC_MBA2 MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE ...
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... Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal MEMC_MCS0 MEMC_MCS1 MEMC_MCKE MEMC_MCK MEMC_MCK MEMC_MODT0 MEMC_MODT1 LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 MPC8313E PowerQUICC Freescale Semiconductor ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal LA24 LA25 LCS0 LCS1 LCS2 LCS3 LWE0/LFWE LWE1 LBCTL LALE/M1LALE/M2LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 LCLK1 LA0/GPIO0/MSRCID0 LA1/GPIO1//MSRCID1 LA2/GPIO2//MSRCID2 LA3/GPIO3//MSRCID3 LA4/GPIO4//MSRCID4 LA5/GPIO5/MDVAL LA6/GPIO6 LA7/GPIO7/TSEC_1588_TRIG2 ...
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... Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal LA14/TSEC_1588_TRIG1 LA15/TSEC_1588_ALARM2 UART_SOUT1/MSRCID0 UART_SIN1/MSRCID1 UART_CTS1/GPIO8/MSRCID2 UART_RTS1/GPIO9/MSRCID3 UART_SOUT2/MSRCID4/TSEC_1588_CLK UART_SIN2/MDVAL/TSEC_1588_GCLK UART_CTS2/TSEC_1588_PP1 UART_RTS2/TSEC_1588_PP2 IIC1_SDA/CKSTOP_OUT/TSEC_1588_TRIG1 IIC1_SCL/CKSTOP_IN/TSEC_1588_ALARM2 IIC2_SDA/PMC_PWR_OK/GPIO10 IIC2_SCL/GPIO11 MCP_OUT IRQ0/MCP_IN IRQ1 IRQ2 IRQ3/CKSTOP_OUT IRQ4/CKSTOP_IN/GPIO12 CFG_CLKIN_DIV EXT_PWR_CTRL CFG_LBIU_MUX_EN TCK TDI TDO MPC8313E PowerQUICC Freescale Semiconductor Package Pin Number L24 ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal TMS TRST TEST_MODE QUIESCE HRESET PORESET SRESET SYS_CR_CLK_IN SYS_CR_CLK_OUT SYS_CLK_IN USB_CR_CLK_IN USB_CR_CLK_OUT USB_CLK_IN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN THERM0 THERM1 PCI_INTA PCI_RESET_OUT PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 MPC8313E PowerQUICC 70 Package Pin Number ...
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... Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_PAR PCI_FRAME MPC8313E PowerQUICC ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_PME TSEC1_COL/USBDR_TXDRXD0 TSEC1_CRS/USBDR_TXDRXD1 TSEC1_GTX_CLK/USBDR_TXDRXD2 TSEC1_RX_CLK/USBDR_TXDRXD3 TSEC1_RX_DV/USBDR_TXDRXD4 TSEC1_RXD3/USBDR_TXDRXD5 TSEC1_RXD2/USBDR_TXDRXD6 TSEC1_RXD1/USBDR_TXDRXD7 TSEC1_RXD0/USBDR_NXT/TSEC_1588_TRIG1 TSEC1_RX_ER/USBDR_DIR/TSEC_1588_TRIG2 TSEC1_TX_CLK/USBDR_CLK/TSEC_1588_CLK TSEC1_TXD3/TSEC_1588_GCLK ...
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... Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal TSEC1_TXD1/TSEC_1588_PP2 TSEC1_TXD0/USBDR_STP/TSEC_1588_PP3 TSEC1_TX_EN/TSEC_1588_ALARM1 TSEC1_TX_ER/TSEC_1588_ALARM2 TSEC1_GTX_CLK125 TSEC1_MDC/LB_POR_CFG_BOOT_ECC_DIS TSEC1_MDIO TSEC2_COL/GTM1_TIN4/GTM2_TIN3/GPIO15 TSEC2_CRS/GTM1_TGATE4/GTM2_TGATE3/GPIO16 TSEC2_GTX_CLK/GTM1_TOUT4/GTM2_TOUT3/GPIO17 TSEC2_RX_CLK/GTM1_TIN2/GTM2_TIN1/GPIO18 TSCE2_RX_DV/GTM1_TGATE2/GTM2_TGATE1/GPIO19 TSEC2_RXD3/GPIO20 TSEC2_RXD2/GPIO21 TSEC2_RXD1/GPIO22 TSEC2_RXD0/GPIO23 TSEC2_RX_ER/GTM1_TOUT2/GTM2_TOUT1/GPIO24 TSEC2_TX_CLK/GPIO25 TSEC2_TXD3/CFG_RESET_SOURCE0 TSEC2_TXD2/CFG_RESET_SOURCE1 TSEC2_TXD1/CFG_RESET_SOURCE2 TSEC2_TXD0/CFG_RESET_SOURCE3 TSEC2_TX_EN/GPIO26 TSEC2_TX_ER/GPIO27 TXA TXA RXA RXA TXB TXB MPC8313E PowerQUICC Freescale Semiconductor ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal RXB RXB SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SDAVDD SD_PLL_TPA_ANA SDAVSS USB_DP USB_DM USB_VBUS USB_TPA USB_RBIAS USB_PLL_PWR3 USB_PLL_GND USB_PLL_PWR1 USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_TIN2/LSRCID0 USBDR_PWRFAULT/GTM1_TGATE1/GTM2_TGATE2/ LSRCID1 USBDR_PCTL0/GTM1_TOUT1/LSRCID2 USBDR_PCTL1/LBC_PM_REF_10/LSRCID3 SPIMOSI/GTM1_TIN3/GTM2_TIN4/GPIO28/LSRCID4 MPC8313E PowerQUICC ...
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... Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal SPIMISO/GTM1_TGATE3/GTM2_TGATE4/GPIO29/ LDVAL SPICLK/GTM1_TOUT3/GPIO30 SPISEL/GPIO31 AV DD1 AV DD2 DDA LV DDB MV REF DDC MPC8313E PowerQUICC Freescale Semiconductor Package Pin Number Power and Ground Supplies F14 P21 A2,A3,A4,A24,A25,B3, B4,B5,B12,B13,B20,B21, B24,B25,B26,D1,D2,D8, D9,D16,D17 D24,D25,G23,H23,R23, T23,W25,Y25,AA22,AC23 W2,Y2 AC8,AC9,AE4,AE5 C14,D14 G4,H4,L2,M2,AC16,AC17, AD25,AD26,AE12,AE13, ...
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... Package and Pin Listings Table 63. MPC8313E TEPBGAII Pinout Listing (continued) Signal V SS XCOREV DD XCOREV SS XPADV DD XPADV SS Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin ...
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... Clocking Figure 57 shows the internal distribution of clocks within the MPC8313E. MPC8313E USB Mac USB PHY PLL mux USB_CLK_IN USB_CR_CLK_IN Crystal /1,/2 USB_CR_CLK_OUT CFG_CLKIN_DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT GTX_CLK125 eTSEC 125-MHz Source Protocol Converter 1 Multiplication factor 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. ...
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... Clocking The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI clock divider (÷ ...
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... TSEC1 TSEC2 2 Security Core SAP, TPR USB DR PCI and DMA complex Table 65 provides the operating frequencies for the MPC8313E TEPBGAII under recommended operating conditions (see Table 2). Table 65. Operating Frequencies for TEPBGAII Characteristic e300 core frequency ( core_clk ) Coherent system bus frequency ( csb_clk ) ...
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... Low 0100 Low 0101 Low 0110 1 CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT. 2 SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8313E PowerQUICC 80 System PLL RCWL[SPMF] Multiplication Factor × 3 0011 × 4 0100 × 5 0101 × 6 0110 0111– ...
Page 81
... Core VCO frequency = core frequency × VCO divider. Note that VCO divider has to be set properly so that the core VCO frequency is in the range of 400–800 MHz. MPC8313E PowerQUICC Freescale Semiconductor shows the encodings for RCWL[COREPLL]. COREPLL values that are NOTE Table 68 ...
Page 82
... USB reference clock must be supplied from a separate source as it must MHz, the USB reference must be supplied from a separate external source using USB_CLK_IN. 21 Thermal This section describes the thermal specifications of the MPC8313E. 21.1 Thermal Characteristics provides the package thermal characteristics for the 516, 27 × TEPBGAII. ...
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... The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8313E PowerQUICC Freescale Semiconductor Board Type Symbol — ...
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... θ θ θ where junction-to-ambient thermal resistance (°C/W) θ junction-to-case thermal resistance (°C/W) θ case-to- ambient thermal resistance (°C/W) θ CA MPC8313E PowerQUICC Ψ ) can be used to determine the junction temperature with ™ II Pro Processor Hardware Specifications, Rev. 3 Freescale Semiconductor ...
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... Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in models can be made available on request. MPC8313E PowerQUICC Freescale Semiconductor . For instance, the user can change the size of the heat R θ ...
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... Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Corporate Center PO BOX 994 Midland, MI 48686-0994 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8313E PowerQUICC 86 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-2800 781-935-4850 800-248-2481 888-642-7674 ™ II Pro Processor Hardware Specifications, Rev. 3 ...
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... From this case temperature, the junction temperature is determined from the junction to case thermal resistance θ where junction temperature (° case temperature of the package junction-to-case thermal resistance θ power dissipation D MPC8313E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 3 800-347-4572 Thermal 87 ...
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... This section provides electrical and thermal design recommendations for successful application of the MPC8313E SYS_CLK_IN 22.1 System Clocking The MPC8313E includes three PLLs. 1. The platform PLL (AV DD2 SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio configuration bits as described in 2 ...
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... Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8313E system, and the MPC8313E itself requires a clean, tightly regulated source of power. Therefore recommended that ...
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... SS 22.6 Output Buffer DC Impedance The MPC8313E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to NV ...
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... Configuration Pin Muxing The MPC8313E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...
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... System Design Information 22.8 Pull-Up Resistor Requirements The MPC8313E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins 2 including I C, Ethernet management MDIO, and IPIC (integrated programmable interrupt controller). Correct operation of the JTAG interface requires configuration of a group of system control pins as ...
Page 93
... Some systems require power to be fed from the application board into the debugger repeater card via the COP header. In this case the resistor value for VDD_SENSE should be around 20 Ω. 2. Key location; pin 14 is not physically present on the COP header. MPC8313E PowerQUICC Freescale Semiconductor PORESET ...
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... RGMII/RTBI interfaces only operate at 2.5 V, not 3.3 V. • Added ZQ package to ordering information In Table 74 and Section 19.1, “Package Parameters for the MPC8313E TEPBGAII” (applicable to both silicon rev. 1.0 and 2.1) • Removed footnotes 5 and 6 from Table 1 (left over when the PCI undershoot/overshoot voltages and maximum AC waveforms were removed from Section 2.1.2, “ ...
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... Added paragraph and Figure 59 to Section 22.2, “PLL Power Supply Filtering.” • Added Section 22.4, “SerDes Block Power Supply Decoupling Recommendations • Removed the two figures on PCI undershoot/overshoot voltages and maximum AC waveforms from Section 2.1.2, “Power Supply Voltage Specification,” MPC8313E PowerQUICC Freescale Semiconductor Substantive Change(s) everywhere ...
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... Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power Sequencing,” and Figure 3. • In Figure 35, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK” • In Table 42, clarified that AC specs are for ULPI only. 0 6/2007 Initial release. MPC8313E PowerQUICC 96 Substantive Change(s) to XCOREVDD XCOREVSS XPADVDD ...
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... Part Numbers Fully Addressed by this Document Table 74 provides the Freescale part numbering nomenclature for the MPC8313E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions ...
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... Figure Notes : MPCnnnnetppaar is the orderable part number. ATWLYYWW is the standard assembly, test, year, and work week codes. CCCCC is the country code. MMMMM is the mask number. Figure 62. Part Marking for TEPBGAII Device MPC8313E PowerQUICC 98 62. MPCnnnnetppaaar core/ddr MHz ATWLYYWW CCCCC MMMMM YWWLAZ TePBGA ™ ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8313E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 3 Ordering Information 99 ...
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... Denver, Colorado 80217 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8313EEC Rev. 3 01/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...