MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 304

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
6.2
Table 6-1
1
2
6.2.1
Arbiter configuration register (ACR) defines the arbiter modes and parked master on the bus.
shows the fields of ACR.
6-2
Offset 0x00
Reset
Reset
Offset (Hex)
Reset value is determined from the core PLL configuration of the reset configuration word. See
and Initialization,”
The registers AEATR and AEADR are affected only by the assertion of PORESET
Memory
W
W
R
R
0x0C
0x1C
0x00
0x04
0x10
0x14
0x18
0x20
1
—
16
0
Note that the reset value of COREDIS and bits 10–11 are determined from reset configuration word. (See
Section 4.3.2, “Reset Configuration Words,”
Arbiter Memory Map/Register Definition
shows the memory map for arbiter’s configuration, control and status registers.
Arbiter Configuration Register (ACR)
Arbiter configuration register (ACR)
Arbiter timers register (ATR)
Arbiter event register (AER)
Arbiter interrupt definition register (AIDR)
Arbiter mask register (AMR)
Arbiter event attributes register (AEATR)
Arbiter event address register (AEADR)
Arbiter event response register (AERR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
17
PCI_RPTCNT
Write accesses to different interfaces are not guaranteed to finish in order.
for details.
—
19
Figure 6-1. Arbiter Configuration Register (ACR)
—
Register
20
Table 6-1. Arbiter Register Map
21
RPTCNT
6
for more details on reset configuration word.)
COREDIS
NOTE
All zeros
23
All zeros
7
1
1
24
8
—
Access
R/W
R/W
R/W
R/W
R/W
w1c
25
R
R
—
26
APARK
0x0010_0000
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000/
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
27
Reset
Chapter 4, “Reset, Clocking,
12
28
Freescale Semiconductor
Access: User read/write
1
2
2
13
PARKM
Section/Page
PIPE_DEP
6.2.8/6-10
Figure 6-1
6.2.1/6-2
6.2.2/6-4
6.2.3/6-5
6.2.4/6-6
6.2.5/6-7
6.2.6/6-7
6.2.7/6-9
15
31