MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 236
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
DDRCDR is shown in
Table 5-31
5-28
10–11
14–29
Offset 0x00128
Reset
Reset
Bits
2–5
6–9
12
13
30
31
0
1
W
W
R
R
DSO_EN
DSO_NZ
DDR_cfg
DSO_PZ
—
Q_DRN
16
0
0
M_odr
Name
shows the bit definition of the DDRCDR.
ODT
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DSO_EN
0
1
Reserved
0 DDR driver software override disable
1 DDR driver software override enable
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
Reserved. Should be cleared.
ODT termination value for I/Os
0 75 Ω
1 150 Ω
Selects voltage level for DDR pads
0 DDR2 (1.8V mode) nominal impedance—18 Ω
1 DDR1 (2.5V mode) nominal impedance—18 Ω
Note: DDR_cfg must be set according to the logical type of the DDR memory devices, as it effects logic
Reserved
Disable memory transaction reordering
0 Memory transaction reordering enabled
1 Memory transaction reordering disabled
0 Drain queue before sleep disable
1 Drain queue before sleep enable
DDR driver software p-impedance override
DDR driver software n-impedance override
Figure
0
2
behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
Figure 5-16. DDR Control Driver Register (DDRCDR)
DSO_PZ
0
5-16.
0
Table 5-31. DDRCDR Field Descriptions
0
5
0
6
DSO_NZ
0
0
—
9
0
All zeros
Description
10
0
—
11
0
ODT
12
0
DDR_cfg
Freescale Semiconductor
13
29
1
Access: Read/Write
M_odr Q_DRN
14
30
0
—
15
31
0
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