MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 792
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 15-46
15.5.3.5.8
The MIIMADD register is written by the user.
Table 15-47
15-74
19–23
24–26
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be
0–29
0–18
Bits
Bits
30
31
Offset eTSEC1:0x2_4528
Reset
W
R
Scan Cycle Scan cycle. This bit is cleared by default.
Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
PHY Address
0
Name
Name
—
describes the fields of the MIIMCOM register.
describes the fields of the MIIMADD register.
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MII Management Address Register (MIIMADD)
Reserved
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
example.
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
Reserved
This field represents the 5-bit PHY address field of Mgmt cycles. Up to 31 PHYs can be addressed
(0 is reserved). Its default value is 0x00.
Reserved
accessed. Its default value is 0x00.
Figure 15-43. MIIMADD Register Definition
Table 15-47. MIIMADD Field Descriptions
Table 15-46. MIIMCOM Descriptions
—
Figure 15-43
All zeros
Description
Description
shows the MIIMADD register.
18 19
PHY Address
23 24
Freescale Semiconductor
—
26 27
Access: Read/Write
Register
Address
31
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