MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 697

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.5.1
14.5.1.1
The crypto-channel configuration register (CCCR) contains five operational bits permitting configuration
of the channel as shown in
Freescale Semiconductor
32–54
0–29
Bits
30
31
55
Reset
Reset
Field
Addr
Field
Addr
R/W
R/W
Names
CON
BS
—
—
32
R
0
Channel Registers
Crypto-Channel Configuration Register (CCCR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, set to zero
Continue bit
0 No special action.
1 Causes the same channel reset actions as bit R, except that the fetch FIFO and the lower half of the CCR
Reset channel
0 No special action.
1 Causes a software reset of the channel, clearing all its internal state. The details of the software reset
Reserved, set to zero
Burst size—The SEC accesses long text-data parcels in main memory through bursts of programmable size:
0 Burst size is 64 bytes
1 Burst size is 128 bytes
register are not cleared. After the reset sequence is complete, this bit automatically returns to 0 and the
channel resumes normal operation, servicing the next descriptor pointer in the fetch FIFO, if any.
actions depend upon what the channel is doing when the bit is set:
• If the R bit is set while the channel is requesting an EU assignment from the controller, the channel
• If the R bit is set after the channel has been assigned an EU, the channel requests a write from the
cancels its request by asserting the release output signals. The channel then resets all its registers,
clears the R bit, and return the channel state machine to the idle state.
controller to set the software reset bit of the EU. If a secondary EU has been reserved, the channel
requests a write to reset that EU as well. The channel next asserts the appropriate release signal to
notify the controller that the channel has finished with the reserved EU(s). The channel then resets all
the registers, clears the RESET bit and returns the channel state machine to the idle state.
Figure 14-36. Crypto-Channel Configuration Register (CCCR)
Figure
—
Table 14-31. CCCR Field Descriptions
14-36.
Table 14-31
54
Channel_1 0x3_110C
Channel_1 0x3_1108
—
BS
55
R/W
R/W
describes the CCR.
0
0
Description
IWSE AWSE EAE CDWE
56
57
58
59
—
60
Security Engine (SEC) 2.2
NT
29
61
CDIE
CON
30
62
—
31
63
R
14-55