MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 985
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Queue element transfer descriptors must be aligned on 32-byte boundaries.
16.5.5.1
The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor.
16.5.5.2
The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the
data stream to the next client buffer on short packet. To be more explicit the host controller will always use
this pointer when the current qTD is retired due to short packet.
Freescale Semiconductor
1
dt
31–5
31–5
31
Bits
Bits
4–1
4–1
Host controller read/write; all others read-only.
1
0
0
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Next qTD
Alternate Next
Pointer
qTD Pointer
Name
—
T
Name
Next qTD Pointer
Alternate Next qTD Pointer
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
T
Total Bytes to Transfer
This field contains the physical memory address of the next qTD to be processed and corresponds to
memory address signals [31:5], respectively.
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
Table 16-54. qTD Alternate Next Element Transfer Pointer (DWord 1)
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
This field contains the physical memory address of the next qTD to be processed in the event that
the current qTD execution encounters a short packet (for an IN transaction). The field corresponds
to memory address signals [31:5], respectively.
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Terminate. Indicates to the host controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid transfer element descriptor)
1 Pointer is invalid
Table 16-53. qTD Next Element Transfer Pointer (DWord 0)
Figure 16-40. Queue Element Transfer Descriptor (qTD)
Alternate Next qTD Pointer
Next qTD Pointer
1
ioc C_Page
15
14 13 12 11 10
Description
Description
1
Cerr
1
Code
9
PID
8
0000_0000_0000
0000_0000_0000
0000_0000_0000
0000_0000_0000
Current Offset
7
6
5
Universal Serial Bus Interface
Status
4
1
0000
0000
3
1
2
1
T 0x00
T 0x04
0
0x0C
0x1C
0x08
0x10
0x14
0x18
offset
16-57
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