MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 855
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.6.1.4
This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the
eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in
1000BASE-SX/LX applications.
signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC
immediately begins auto-negotiation with the SerDes.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the gigabit Ethernet controllers module
connections in the system, assuming that each PHY has a different management address.
eTSEC
Reduced Ten-Bit Interface (RTBI)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transmit Data (TSECn_TXD[3:0]
Receive Data (TSECn_RXD[3:0]
Transmit Control (TX_EN/f(TX_EN,TX_ER))
Receive Control (RX_DV/f(RX_DV,RX_ER))
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Figure 15-129. eTSEC-RGMII Connection
Figure 15-130
Receive Clock (TSEC n _RX_CLK)
Management Data Clock
Management Data I/O
depicts the basic components of the RTBI including the
1
1
(MDIO)
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
Gigabit
PHY
Medium
15-137
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