MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 422
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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DDR Memory Controller
9.4.1.15
The DDR SDRAM initialization address register, shown in
for the automatic CAS to preamble calibration after POR.
Table 9-21
9.4.1.16
The DDR IP block revision 1 register, shown in
ID, along with major and minor revision information.
Table 9-22
9-28
1
Offset 0xBF8
Reset n
16–23
24–31
Offset 0x148
Reset
0–31
0–15
Bits
Bits
For reset values, see
W
W
R
R
0
0
1
IP_MN Minor revision. This is currently set to 0x01.
INIT_ADDR Initialization address. Represents the address that is used for the automatic CAS to preamble calibration
IP_MJ Major revision. This is currently set to 0x02.
Name
IP_ID
n
Name
describes the DDR_INIT_ADDR fields.
describes the DDR_IP_REV1 fields.
Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
DDR Initialization Address (DDR_INIT_ADDR)
DDR IP Block Revision 1 (DDR_IP_REV1)
n
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
IP block ID. For the DDR controller, this value is 0x0002.
n
n
at POR.
Table 9-22
n
n
Figure 9-17. DDR IP Block Revision 1 (DDR_IP_REV1)
IP_ID
n
Table 9-21. DDR_INIT_ADDR Field Descriptions
.
Table 9-22. DDR_IP_REV1 Field Descriptions
n
n
n
n
n
n
Figure
n
INIT_ADDR
All zeros
15 16
n
Description
9-17, provides read-only fields with the IP block
n
Description
Figure
n
n
IP_MJ
n
9-16, provides the address that is used
n
n
n
23 24
n
n
Freescale Semiconductor
n
n
Access: Read/Write
Access: Read Only
IP_MN
n
n
n
n
31
31
n
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