MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1035
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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There exists a one-to-one relationship between a high-speed isochronous split transaction (including all
start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other
things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one
full-speed isochronous data payload. This means that for any full-speed transaction payload, a single
siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information
usually also maps to one high-speed isochronous split transaction. The exception to this rule is the
H-Frame boundary wrap cases mentioned above.
The siTD data structure describes at most, one frame's worth of high-speed transactions and that
description is strictly bounded within a frame boundary.
top are examples of the full-speed transaction footprints for the boundary scheduling cases described
above. In the middle are time-frame references for both the B-Frames (HS/FS/LS Bus) and the H-Frames.
On the bottom is illustrated the relationship between the scope of an siTD description and the time
references. Each H-Frame corresponds to a single location in the periodic frame list. The implication is
that each siTD is reachable from a single periodic frame list location at a time.
Each case is described below:
Freescale Semiconductor
•
•
H-Frame
4
5
Case 1: One siTD is sufficient to describe and complete the isochronous split transaction because
the whole isochronous split transaction is tightly contained within a single H-Frame.
Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always take only one
siTD to schedule. However, INs (for these boundary cases) require two siTDs to complete the
scheduling of the isochronous split transaction. siTDX is used to always issue the start-split and
the first N complete-splits. The full-speed transaction (for these cases) can deliver data on the
full-speed bus segment during micro-frame 7 of H-Frame
The complete splits are scheduled using siTD
data must use the buffer pointer from siTD
siTD
B-Frame
5
6
Y–1
X+1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6
7
Y–1
from H-Frame
7
0
0
1
Case 1
1
2
Figure 16-58. siTD Scheduling Boundary Examples
H-Frame
2
3
Y+2
siTD
B-Frame
4
3
is to use siTD
X
Y
4
5
Full-Speed Transaction
Y
Case 2a
5
6
Back Pointer
6
7
X+2
X+1
7
0
's back pointer.
X+2
. The only way for the host controller to reach
0
1
Figure 16-58
(not shown). The complete-splits to extract this
1
2
H-Frame
2
3
siTD
B-Frame
Y+1
Case 2b
4
X+1
3
, or micro-frame 0 of H-Frame
Y+1
illustrates some examples. On the
4
5
Y+1
5
6
6
7
Universal Serial Bus Interface
7
0
H-Frame
0
1
B-Frame
1
2
Y+2
2
3
Y+2
Y+2
16-107
.
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