MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1169

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.4.4.1. 10-78
10.4.4.4.5, 10-83
10.4.4.4.7, 10-84
MxMR[AM] = 000
Freescale Semiconductor
AMX = 10
AMX = 00
(Row)
(Col)
ms
b
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
2
3
By default, all local bus refreshes are performed using the refresh pattern of
UPMA. This means that if refresh is required, MAMR[RFEN] must be set. It also
means that only one refresh routine should be programmed and be placed in
UPMA, which serves as the refresh executor. Any banks assigned to a UPM are
provided with the common UPMA refresh pattern if the RFEN bit of the
corresponding UPM is set, concurrently. UPMA assigned banks, therefore, always
receive refresh services when MAMR[RFEN] is set, while UPMB and UPMC
assigned banks also receive (the same) refresh services if the corresponding
MxMR[RFEN] bits are set. In this scenario, more than one chip select may assert
at the same time, as refresh pattern runs for all banks assigned to UPM with RFEN
bit set.
In Table 10-38, bit 24 and bits 26–27, added the following at the end of each
description:
Note: AMX must not change values in any RAM word which begins a loop.
In bits 24 and 31, added the following at the end of each description:
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
In the second paragraph, replace the last sentence and add two bullets as follows:
Also, special care must be taken:
• LAST and LOOP must not be set together.
• Loop start word should not have an AMX change with regard to the previous
Replaced the first two paragraphs and Table 10-40 with the following:
The address lines can be controlled by the pattern the user provides in the UPM.
The address multiplex (AMX) bits in the RAM word can choose between driving
the transaction address (AMX = 00), driving it according to the multiplexing
specified by the MxMR[AM] field (AMX = 10), or driving the contents of MAR
(AMX = 11) on the address signals. In all cases, LA[21:25] of the eLBC are driven
by the five lsbs of the address selected by AMX, regardless of whether the next
address (NA) bit of the RAM word is used to increment the current address. The
effect of NA = 1 is visible only when AMX = 00 chooses the column address.
Table 10-40 shows how the RAM word AMX bits and MxMR[AM] settings can
be used to affect row × column address multiplexing on the LA[10:25] signals.
4
word.
5
6
Table 10-40. UPM Address Multiplexing
7
10 11 12 13 14 15 16 17 18 19 20 21 22
8
9
10 11 12 13 14 15 16 17 18 19 20
LAD
Internal Transaction Address
LA
21
23
22 23 24 25 26 27 28 29 30 31
24 25
18 19 20 21 22 23 24 25
Revision History
LA
A-11
lsb