MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 303

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Chapter 6
Arbiter and Bus Monitor
This chapter describes operation theory of the arbiter in the device. In addition, it describes configuration,
control, and status registers of the arbiter.
6.1
The arbiter is responsible for providing coherent system bus arbitration. It tracks all address and data
tenures and provides all the arbitration signals to masters and slaves. In addition, it monitors the bus and
reports on errors and protocol violations.
The arbiter includes the following features:
6.1.1
The coherent system bus is the central bus of the device. Any data transaction from master to slave in the
device passes through the coherent system bus. The device coherent system bus supports pipelined
transactions. It has independent address and data tenures. Pipeline depth determines the number of address
tenures that can be started before the first data tenure is finished.
Basic burst size is equal to cache line length of the core, which is 32 bytes. Using repeat request mode
enables up to eight consecutive bursts to be executed by the same master. Maximum number of
consecutive transactions can be limited by programming arbiter configuration register. See
“Arbiter Configuration Register (ACR),”
Freescale Semiconductor
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Supports a programmable pipeline depth (from 1 to 4)
Supports four levels of priority for bus arbitration
Supports repeat-request mode: number of programmable consecutive transactions from the same
master (up to eight transactions)
Supports data streaming operations
Supports programmable address bus parking mode: disable, park to last bus owner, park to
software selected master
Claims address only, reserved and illegal transaction types, report on it and can raise maskable
interrupt
Provides timers for address tenure time out and data tenure time out detection and can issue
maskable interrupt, if any timer expired
Reports on transfer error and can issue maskable interrupt
Can issue regular or machine check interrupt for each type of error event (programmable)
Overview
Coherent System Bus Overview
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for more details.
Section 6.2.1,
6-1