MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 844

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.4.3.3
Figure 15-119
Table 15-128
15-126
Bits
Bits
2–3
12
13
14
15
0
1
Offset 0x04
Reset
W
R
Remote
Extend
Status
Name
Name
Ability
Ability
Page
Next
Fault
Link
Page
AN
Next
—
—
0
describes the fields of the ANA register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the ANA register.
AN Advertisement Register (ANA)
Next page configuration. The local device sets this bit to either request next page transmission or advertise
next page exchange capability.
0 The local device wishes not to engage in next page exchange.
1 The local device has no next pages but wishes to allow reception of next pages. If the local device has no
Reserved. (Ignore on read)
The local device’s remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in
the following table. The default value is 00. Indicate a fault by setting a non-zero remote fault encoding and
re-negotiating.
Auto-negotiation ability. While read as set, this bit indicates that the PHY has the ability to perform
auto-negotiation. While read as cleared, this bit indicates the PHY lacks the ability to perform
auto-negotiation. Returns 1 on read. This bit is read-only.
Link status. This bit is read-only and is cleared by default.
0 A valid link is not established. This bit latches low allowing for software polling to detect a failure condition.
1 A valid link is established.
Reserved, should be cleared.
Extended capability. This bit indicates that the PHY contains the extended set of registers (those beyond
control and status). Returns 1 on read. This bit is read-only.
—
1
next pages and the link partner wishes to send next pages, the local device shall send null message
codes and have the message page set to 0b000_0000_0001, as defined in annex 28C.
Remote Fault
2
Figure 15-119. AN Advertisement Register Definition
RF1 bit[3]
0
0
1
1
Table 15-127. SR Descriptions (continued)
3
Table 15-128. ANA Field Descriptions
4
RF2 bit[2]
—
0
1
0
1
6
No error, link OK
Offline
Link_Failure
Auto-Negotiation_Error
Pause
7
All zeros
Description
Description
8
Duplex
Half
Description
9
Duplex
Full
10
11
Freescale Semiconductor
Access: Read/Write
—
15