MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 663
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 14-12
14.4.1.3
The DEU data size register (DEUDSR), shown in
message block, which must be 64. All data to be processed by the DEU must be a multiple of the DES
algorithm block size of 64 bits; the DEU does not automatically pad messages out to 64-bit blocks. If a
data size that is not a multiple of 64 bits is written, a data size error will be generated. Only bits 58–63 are
checked to determine if there is a data size error. Since all upper bits are ignored, the entire message length
(in bits) can be written to this register.
DEUDSR is cleared when the DEU is reset or re-initialized.
Freescale Semiconductor
52–63
0–51
Bits
Reset
Reset
Field
Field
Addr
Addr
R/W
R/W
Key Size
Name
—
shows the DEUKSR fields.
DEU Data Size Register (DEUDSR)
0
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
8 bytes = 0x08 (only legal value if mode is single DES)
16 bytes = 0x10 (for 2 key 3DES, K1 = K3)
24 bytes = 0x18 (for 3 key 3DES)
Figure 14-9. DEU Data Size Register (DEUDSR)
Figure 14-8. DEU Key Size Register (DEUKSR)
Table 14-12. DEUKSR Field Descriptions
—
—
DEU 0x3_2008
DEU 0x3_2010
Figure
R/W
R/W
0
0
Description
14-9, stores the number of bits in the final
51
51
52
52
Key Size (bytes)
Data Size (bits)
Security Engine (SEC) 2.2
63
63
14-21
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