MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 350

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

e300 Processor Core Overview
The e300 core interrupts and exception conditions that cause them are listed in
7-32
Reserved
System reset
Machine check
DSI
ISI
External interrupt
Alignment
Interrupt Type
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
00000
00100
00200
00300
00400
00500
00600
Vector Offset
(hex)
Caused by the assertion of either hreset.
Caused by the assertion of the tea signal during a data bus transaction, assertion of mcp ,
an address or data parity error, or an instruction or data cache parity error. Note that the
e300 has SRR1 register values that are different from the G2/G2_LE cores’ when a
machine check occurs.
Determined by the bit settings in the DSISR, listed as follows:
1
4
6
9
Caused when an instruction fetch cannot be performed for any of the following reasons:
Caused when MSR[EE] = 1 and the int signal is asserted.
Caused when the core cannot perform a memory access for any of the reasons described
below:
• The effective (logical) address cannot be translated. That is, there is a page fault for this
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key bits
• The operand of a floating-point load or store instruction is not word-aligned.
• The operands of lmw, stmw, lwarx, and stwcx. instructions are not aligned.
• The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note
• The operand of dcbz is in memory that is write-through-required or caching-inhibited.
portion of the translation, so an ISI interrupt must be taken to load the PTE (and possibly
the page) into memory.
(Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read
access, instructions cannot be fetched from this location.
that PowerPC little-endian mode is not supported on the e300 core.
Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register;
otherwise cleared
Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
Set for a store operation and cleared for a load operation
Set if a data address breakpoint interrupt occurs when the data [0–28] in the DABR or
DABR2 matches the next data access (load or store instruction) to complete in the
completion unit. The different breakpoints are enabled as follows:
• Write breakpoints enabled when DABR[30] is set
• Read breakpoints enabled when DABR[31] is set
Table 7-7. Exceptions and Interrupts
Exception Conditions
—
Table
Freescale Semiconductor
7-7.