MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 599
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 13-9
13.3.2.3
PCI_EER contains fields for enabling the assertion of an interrupt for the error conditions reported in the
PCI error status register (PCI_ESR).
Figure 13-7
Table 13-10
Freescale Semiconductor
Offset 0x08
Reset
W
•
•
0–20
R
Bits
21
22
23
24
25
0
1 = The interrupt is enabled.
0 = The interrupt is disabled.
27–31
describes the bit settings of the PCI_ECDR register.
0–20
Bits
21
22
23
24
25
26
shows the PCI_EER fields.
describes the bit settings of the PCI_EER register.
PCISERR PCI system error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
MPERR
PCI Error Enable Register (PCI_EER)
NORSP
TPERR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
APAR
—
PCISERR PCI system error. Disable capture for received PCI_SERR errors
MPERR
NORSP
TPERR
Name
APAR
TABT
Reserved
Address parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Master parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Target parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
No response. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
—
—
—
Figure 13-7. PCI Error Enable Register (PCI_EER)
Reserved
Address parity error. Disable capture for address parity errors
Target abort. Disable capture for target abort errors
Reserved
Master parity error. Disable capture for master PCI_PERR errors
Target parity error. Disable capture for target PCI_PERR errors
No response. Disable capture for master-abort errors
Table 13-9. PCI_ECDR Field Descriptions
Table 13-10. PCI_EER Field Descriptions
20
APAR PCISERR MPERR TPERR NORSP TABT
21
All zeros
Description
Description
22
23
24
25
Access: Read/Write
26
PCI Bus Interface
27
—
13-17
31
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