MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 164
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Signal Descriptions
3-30
1
2
USBDR_STP_SUSPEND
State of TSEC1_TXD0 depends on RTBI mode in TSEC1M bits in RCWH. Its state changes from 1 to 0 after RCWH is
loaded during reset sequence.
This pin should be pulled high during a hard reset for proper functionality of the device since it has a weak internal pull up.
No external pull-down resistors are allowed to be mounted on this net.
TSEC1_TXD[3:0]
LWE0/LFWE/LBS0
TSEC1_GTX_CLK
TSEC2_GTX_CLK
PCI_RESET_OUT
LOE/LGPL2/LFRE
UART_SOUT[0:1]
TSEC2_TXD[3:0]
PCI_SYNC_OUT
USBDR_PCTL0
USBDR_PCTL1
UART_RTS[0:1]
TSEC1_TX_EN
PCI_GNT[0:2]
TSEC_MDC
LWE1/LBS1
MCP_OUT
LCLK[0:1]
QUIESCE
PCI_INTA
Interface
LA[16:25]
LBCTL
LCS0
LCS1
LALE
TDO
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 3-4. Output Signal States During System Reset (continued)
1
2
PCI interrupt output
PCI reset output
PCI grant 0–2
DUART serial data out
DUART ready to send
eTSEC1 transmit clock out
eTSEC1 transmit data 2–0
eTSEC1 transmit enable
eTSEC2 transmit clock out
eTSEC2 transmit data 6-4
Ethernet management data clock
eLBC port address
eLBC chip select 0
eLBC chip select 1
eLBC write enable 0/FCM write enable
0/UPM byte (lane) select 0
eLBC write enable 1/UPM byte (lane)
select 1
eLBC data buffer control
eLBC address latch enable
eLBC output enable/GP line 2/FCM read
enable
eLBC clock
USB port control 0
USB port control 1
Machine check interrupt output
Test data out
Quiesce state
PCI sync output
USB host 0 data stop/suspend
Signal
Active—used to load reset configuration word
Active—used to load reset configuration word
Active—used to load reset configuration word
Active—used to load reset configuration word
Active—used to load reset configuration word
State During Reset
Active clock
All ‘Z’
All ‘Z’
All ‘Z’
All ‘Z’
All ‘Z’
All ‘0’
‘Z’
‘0’
‘0’
‘0’
’Z’
‘0’
‘1’
‘1’
‘1’
’1’
’0’
‘Z’
‘Z’
‘1’
Z
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