MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 722
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Three-Speed Ethernet Controllers
15.3
The eTSEC’s primary operational modes are the following:
15-4
•
•
•
•
— Broadcast address (accept/reject)
— Hash table match on up to 256 unicast/multicast or 512 multicast-only addresses
— Promiscuous mode
Remote network monitoring (RMON) statistics support
— 32-bit byte counters
— Carry/Overflow of counter interrupts
Backward compatibility with MPC8349E (PowerQUICC II Pro) TSEC
— PowerQUICC II Pro buffer descriptor (BD) format and rings supported
— Common register memory map, with specific exceptions:
— Reset state of eTSEC defaults to common PowerQUICC II Pro TSEC subset
— TSEC_ID register permits TSEC versus enhanced TSEC differentiation
Hardware assist for 1588 compliant timestamping
— Per packet timestamp tag for Receive
— Programmable timestamp capture for Transmit
— Recognition of PTP packet
— Periodic Pulse Generation
— Self-correcting precision timer with nano-second resolution
— Phase aligned adjustable (divide by N) clock output
— Two 64-bit alarm (future time) registers for future time comparison
This is determined by the MACCFG2 register’s full-duplex bit (MACCFG2[Full Duplex]).
Full-duplex mode is intended for use on point-to-point links between switches or end node to
switch. Half-duplex mode is used in connections between an end node and a repeater or between
repeaters.
If configured in half-duplex mode (10- and 100-Mbps operation; MACCFG2[Full Duplex] is
cleared), the MAC complies with the IEEE CSMA/CD access method.
If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set),
the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send
PAUSE frames.
Full- and half-duplex operation
Modes of Operation
– In addition to primary station address, up to fifteen additional exact-match MAC addresses
– Out-of-sequence transmit BD not supported
– Internal DMA BD pointers and data counts not visible
– MINFLR register not supported
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
supported
Freescale Semiconductor
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