MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 479
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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10.3.1.15 Local Bus Configuration Register (LBCR)
The local bus configuration register (LBCR) is shown in
Freescale Semiconductor
Offset 0x0_50D0
Reset
Reset
Offset 0x0_50C4
Reset
12–15
16–27
28–31
0–11
W
W
Bits
R
R
W
R
LDIS
16
0
0
0
MBUE Multi bit uncorrectable error
Name
SBCE Single bit correctable error
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
1
Reserved
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had a single bit correctable ECC error on read (bit 12 represents block 0, the first
512 bytes of a page; if ORx[PGS] = 0, bits 13–15 are always 0).
Reserved
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had an uncorrectable ECC error on read (bit 28 represents block 0, the first 512
bytes of a page; if ORx[PGS] = 0, bits 29–31 are always 0).
0
—
0
Figure 10-18. Transfer Error ECC Register (LTECCR)
BMT
Figure 10-19. Local Bus Configuration Register
—
Table 10-21. LTECCR Field Descriptions
0
0
11 12
0
SBCE
23
0
7
All zeros
All zeros
15 16
Description
24
8
0
Figure
BCTLC
0
9
10-19.
—
AHD
10
0
11
27
0
—
28
0
Enhanced Local Bus Controller
1
—
BMTPS
Access: Read/Write
27 28
Access: w1c
0
MBUE
10-31
15
31
0
31
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