MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 426
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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DDR Memory Controller
9.5.1
The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with
different sizes can be used in the same system. Fifteen multiplexed address signals and three logical bank
select signals support device densities from 64 Mbits to 2 Gbits. Two chip select (CS) signals support one
bank of memory. The DDR SDRAM physical banks can be built from standard memory modules or
directly-attached memory devices. The data path to individual physical banks is bits wide. The DDR
memory controller supports physical bank sizes from 16 Mbytes to 512 Mbytes. The physical banks can
9-32
1. All signals are connected in common (in parallel) except for MCS[0:1], MCK, MDM[0:3], and the data bus signals.
2. Each of the MCS[0:1] signals correspond with a separate physical bank of memory.
3. Buffering may be needed if large memory arrays are used.
DDR
Controller
MDQS[0:3]
MDQ[0:31]
MDM[0:3]
MBA[2:0]
MCS[0:1]
MA[14:0]
MRAS
MCAS
MCKE
MWE
MCK
MCK
DDR SDRAM Interface Operation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-22. Example 64-Mbyte DDR SDRAM Configuration
0
1
2
3
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
8M×8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
2 Mx8 SDRAM
DQ[7:0]
DQ[0-7]
MDQS
2 Bank’s of 8M ×32 (32 Mbytes each)
DQ(7-0)
DQ(7-0)
To all SDRAM
Devices in
Common
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQS[3]
MDQS[0]
Memory Data Bus and Strobes
0
1
2
3
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
8M×8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
2Mx8 SDRAM
DQ[7:0]
DQ[0-7]
MDQS
DQ(7-0)
DQ(7-0)
Freescale Semiconductor
MDQS[0]
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQS[3]
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