MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 383

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

8.5.16
Each implemented bit SIFCR_H and SIFCR_L, shown in
internal interrupt source. When a bit is set, the interrupt controller generates the corresponding interrupt
(sets the corresponding SIPNR bit).The SIFCR can be read by the user at any time.
Table 8-25
SIFCR_L is shown in
Table 8-26
Freescale Semiconductor
Offset 0x50
Offset 0x54
Reset
Reset
0–31
Bits
0–31
Bits
W
W
R
R
0
0
Name
INT n Each implemented bit, listed in
Name
INT n Each implemented bit, listed in
defines the bit fields of SIFCR_H.
defines the bit fields of SIFCR_L.
System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
interrupt by setting the corresponding SIFCR x bit. SIFCR n bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0
interrupt by setting the corresponding SIFCR x bit. SIFCR x bit positions are not changed according to their
relative priority.
Writes to unimplemented (reserved) bits are ignored; read = 0
Figure 8-19. System Internal Interrupt Force Register (SIFCR_H)
Figure 8-20. System Internal Interrupt Force Register (SIFCR_L)
Figure
8-20.
Table 8-25. SIFCR_H Field Descriptions
Table 8-26. SIFCR_L Field Descriptions
INT n (Implemented bits are listed in
INT
n (Implemented bits are listed in
Table
Table
8-7, corresponds to an internal interrupt source. The user forces an
8-9, corresponds to an internal interrupt source. The user forces an
All zeros
All zeros
Description
Description
Figure 8-19
Integrated Programmable Interrupt Controller (IPIC)
Table
Table
and
8-7.)
8-9).
Figure
8-20, corresponds to an
Access: Read/write
Access: Read/write
8-25
31
31