MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 462
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
10-14
21–22
24–27
Bits
23
28
29
Name
XACS Extra address to chip-select setup. Setting this bit increases the delay of the LCS n assertion relative to the
TRLX
SETA
ACS
SCY
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Address to chip-select setup. Determines the delay of the LCS n assertion relative to the address change
when the external memory access is handled by the GPCM. At system reset, OR0[ACS] = 11
address change when the external memory access is handled by the GPCM. After a system reset,
OR0[XACS] = 1.
0 Address to chip-select setup is determined by ORx[ACS] and LCRR[CLKDIV].
1 Address to chip-select setup is extended (see
Cycle length in bus clocks. Determines the number of wait states inserted in the bus cycle, when the GPCM
handles the external memory access. Thus it is the main parameter for determining cycle length. The total
cycle length depends on other timing attribute settings. After a system reset, OR0[SCY] = 1111.
0000 No wait states
0001 1 bus clock cycle wait state
...
1111 15 bus clock cycle wait states
External address termination.
0 Access is terminated internally by the memory controller unless the external device asserts LGTA earlier
1 Access is terminated externally by asserting the LGTA external pin. (Only LGTA can terminate the access).
Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals.
0 Normal timing is generated by the GPCM.
1 Relaxed timing on the following parameters:
• Adds an additional cycle between the address and control signals (only if ACS is not equal to 00).
• Doubles the number of wait states specified by SCY, providing up to 30 wait states.
• Works in conjunction with EHTR to extend hold time on read accesses.
• LCS n (only if ACS is not equal to 00) and LWE signals are negated one cycle earlier during writes.
to terminate the access.
[CLKDIV]
LCRR
4 or 8
Table 10-7. OR
2
x
Value
00
01
10
11
10
11
n
—
LCS n is output at the same time as the address lines. Note that this
overrides the value of CSNT such that CSNT = 0.
Reserved.
LCS n is output one half bus clock cycle after the address lines.
LCS n is output one half bus clock cycle after the address lines.
LCS n is output one quarter bus clock cycle after the address lines.
LCS n is output one half bus clock cycle after the address lines.
GPCM Field Descriptions (continued)
Description
Table 10-32
and
Meaning
Table
10-33).
Freescale Semiconductor
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