MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 537

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.5.1.3
With the use of a feature called address byte swap by setting LBCR[ABSWP], data and address muxing
can be swapped from the default available. Currently, LAD[0:31] carries A[0:31]. In case of 8-bit interface
with 8-bit addressing we do not get benefit of pin reduction with the available muxing. This is because,the
MSB of data is muxed with MSB of address. While 8-bit data required is LAD[0:7] and address required
is lower order bits A[24:31] we need to pull out all the 16 bits out of the device. For pin limited devices,
this feature can be used where LAD[0:7] is mapped to the lsb’s of A[24:31] and LAD[8:15] carries lsb+1
[16:23]. As a result while interfacing with 8 bit address and 8-bit data only LAD[0:7] is suffice with LALE
pin. The only drawback of this feature is that it does not support burst as all the address is latched from
LAD bus.
10.5.1.4
To achieve the highest possible bus speeds on the local bus, it is recommended to reduce the number of
devices connected directly to the bus. For best results, only one bank of synchronous SRAMs should have
a direct connection, and a bus demultiplexor should be used to replace separate latch and separate bus
transceiver combinations.
guideline, and the board designer must simulate the electric characteristics of the scenario to determine the
maximum operating frequency.
Freescale Semiconductor
Multiplexed Address and Data to Save Maximum Pins in 8- to 16-Bit
Addressing
Peripheral Hierarchy on the Local Bus for High Bus Speeds
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Local Bus Interface
LAD[
Figure 10-70. Non-Multiplexed Address and Data Buses
LA[0:25]
Figure 10-71
LALE
0:15
]
N.C.
shows an example of such a hierarchy. This section is only a
Muxed Address/Data
Unmuxed Address
D[15:0]
A[0:25]
Device
Enhanced Local Bus Controller
10-89