MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 631

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.4.3.6
The timing diagrams in this section show the relationship of significant signals involved in bus
transactions.
Note the following conventions:
13.4.3.7
Both read and write transactions begin with an address phase followed by a data phase. The address phase
occurs when PCI_FRAME is asserted for the first time, and the AD[31:0] signals contain a byte address
and the PCI_C/BE[3:0] signals contain a bus command. The data phase consists of the actual data transfer
and possible wait cycles; the byte enable signals remain actively driven from the first clock of the data
phase through the end of the data transfer.
A read transaction starts when PCI_FRAME is asserted for the first time and the PCI_C/BE[3:0] signals
indicate a read command.
Freescale Semiconductor
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When a signal is drawn as a solid line, it is actively being driven by the current initiator or target.
When a signal is drawn as a dashed line, no agent is actively driving it.
Three-stated signals with slashes between the two rails have indeterminate values.
The terms ‘edge’ and ‘clock edge’ refer to the rising edge of the clock.
The terms ‘asserted’ and ‘negated’ refer to the globally visible state of the signal on the clock edge,
and not to signal transitions.
The symbol
PCI_C/BE[3:0]
Bus Transactions
Read and Write Transactions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI_DEVSEL
PCI_AD[31:0]
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_CLK
represents a turnaround-cycle.
Figure 13-48
ADDR
CMD
Figure 13-48. Single Beat Read Example
shows an example of a single beat read transaction.
BYTE ENABLES
DATA
PCI Bus Interface
13-49