MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 654

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14-12
12–15
16–23
24–28
4–11
Bits
0–3
29
30
31
Writeback
Writeback
Field
Field
Bit #
Bit #
OP_0:
OP_1:
DESC_TYPE
EU_SEL0
EU_SEL1
MODE0
MODE1
Name
32 34 35 36 37
EU_SEL0
DIR
DN
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
0
DONE
3
ICR0
OP_0
Primary EU select. See
possible values.
Primary mode. Mode data used to program the primary EU. The mode data is to the chosen EU.
This field is passed directly to bits 56–63 of the mode register in the selected EU.
Secondary EU select. See
for possible values.
Secondary mode. Mode data used to program the primary EU. The mode data is to the chosen EU.
This field is passed directly to bits 56–63 of the mode register in the selected EU.
Descriptor type. This, along with the DIR field, determines the sequence of actions to be performed
by the channel and selected EUs using the blocks of data listed in the rest of the descriptor. The
attributes determined include the direction of data flow for each data block, which EU (primary or
secondary) is accessed, what snooping options are used, and which internal EU addresses are
accessed.
See
Reserved.
Direction. Direction of overall data flow
0 Outbound
1 Inbound
This, along with the DESC_TYPE field, helps determine the sequence of actions to be performed
by the channel and selected EUs.
Done notification.
0 No done notification.
1 Signal ‘done’ to the host on completion of this descriptor.
This enables done notification if the NT field is 1 in the channel configuration register (see
Table
of this header dword (see
Done Interrupt Enable) and CDWE (Channel Done Writeback Enable) bits in the channel
configuration register.
4
MODE0
Section 14.3.2.2, “Selecting Descriptor Type—DESC_TYPE,”
7
14-31). The done notification can take the form of an interrupt, a writeback in the DONE field
—
42
8
Table 14-4. Header Dword Bit Definitions
11 12
43 44
ICR1
EU_SEL1
Figure 14-4. Header Dword
Section 14.3.2.1, “Selecting Execution Units—EU_SEL0 and EU_SEL1,”
15
45
Table
Section 14.3.2.1, “Selecting Execution Units—EU_SEL0 and EU_SEL1,”
OP_1
14-5), or both, depending upon the states of the CDIE (Channel
16
MODE1
—
Description
23
—
24
DESC_TYPE
—
for possible values.
28
Freescale Semiconductor
29
—
DIR
30
DN
31
63
for