MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 678

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.4.2.8
The MDEU interrupt control register (MDEUICR), shown in
errors. For a given error (as defined in
if the corresponding bit in this register is set, then the error is disabled; no error interrupt occurs and the
MDEU interrupt status register (MDEUISR) is not updated to reflect the error. If the corresponding bit is
not set, then upon detection of an error, the interrupt status register is updated to reflect the error, causing
assertion of the error interrupt signal, and causing the module to halt processing.
14-36
58–60
62–63
Bits
53
54
55
56
57
61
Reset
Field
Addr
R/W
Name
KSE
DSE
IFO
ME
CE
AE
—
—
MDEU Interrupt Control Register (MDEUICR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Context error. The MDEU key register, key size register, or data size register was modified while MDEU was
hashing.
0 No error detected
1 Context error
Key size error. A value greater than 64 bytes was written to the MDEU key size register (MDEUKSR).
0 No error detected
1 Key size error
Data size error. A value not a multiple of 512 bits while the MDEU mode register (MDEUMR) CONT bit is high.
0 No error detected
1 Data size error
Mode error. Will be set if any of these error conditions is detected:
0 No error detected
1 Mode error
Address error. An illegal read or write address was detected within the MDEU address space.
0 No error detected
1 Address error
Reserved
Input FIFO overflow. The MDEU input FIFO has been pushed while full.
0 No overflow detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
Reserved
• Any reserved bit of the mode register is set
• The ALG field of the mode register contains an illegal value
is not a limit to data input size. When operated through host-controlled access, the MDEU cannot
accept FIFO inputs larger than 256 bytes without overflowing.
Figure 14-22. MDEU Interrupt Control Register (MDEUICR)
—
Table 14-23. MDEUISR Field Descriptions (continued)
48
Section 14.4.2.7, “MDEU Interrupt Status Register
ICE
49
—
50
MDEU 0x3_6038
51
IE ERE CE KSE DSE ME AE
0x3000
R/W
Description
52
53
Figure
54
14-22, controls the result of detected
55
56
57
58
Freescale Semiconductor
—
60
(MDEUISR)”),
IFO
61
62
—
63