MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 789

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.5.4
The HAFDUP register is written by the user.
Table 15-43
Freescale Semiconductor
16–23
25–31
Offset eTSEC1:0x2_450C; eTSEC2:0x2_550C
9–15
Reset
Reset
8–11
Bits
Bits
0–7
24
12
13
W
W
R
R
Inter-Packet-Gap, Part 2
Retransmission Maximum
16
0
0
1
Alternate BEB
Non-Back-to-Back
Truncation
Inter-Packet-Gap
BackOff
Alt BEB
describes the fields of the HAFDUP register.
BP No
Minimum IFG
Back-to-Back
Name
Enforcement
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Half-Duplex Register (HAFDUP)
Name
0
1
—
0
1
Reserved
This field is used while ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set. The
value programmed is substituted for the Ethernet standard value of ten. Its default is 0xA.
Alternate binary exponential backoff. This bit is cleared by default.
0 The Tx MAC follows the standard binary exponential back off rule.
1 The Tx MAC uses the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting
Back pressure no backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation.
—
instead of the 802.3 standard tenth collision. The standard specifies that any collision after the
tenth uses one less than 210 as the maximum backoff time.
Table 15-42. IPGIFG Field Descriptions (continued)
19
0
1
This is a programmable field representing the non-back-to-back inter-packet-gap in bits. Its
default is 0x60 (96d), which represents the minimum IPG of 96 bits.
This is a programmable field representing the minimum number of bits of IFG to enforce
between frames. A frame is dropped whose IFG is less than that programmed. The default
setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits.
Reserved
This is a programmable field representing the IPG between back-to-back packets. This is
the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two
transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired.
The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.
Figure 15-39. Half-Duplex Register Definition
Table 15-43. HAFDUP Field Descriptions
20
0
0
0
0
0
0
—
0
0
7
Figure 15-39
Alternate BEB
8
1
0
Truncation
25
0
0
26
1
1
11
0
1
describes the HAFDUP register.
Description
Alt BEB BP No BackOff No BackOff Excess Defer
Description
12
0
0
Enhanced Three-Speed Ethernet Controllers
Collision Window
13
0
1
14
0
1
Access: Read/Write
15
31
1
1
15-71